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9.3.2.2 External Board Loopback

• The OSPI[x]_CLK output pin must be connected to the CLK input pin of the attached OSPI/QSPI/SPI device

• The OSPI[x]_LBCLKO output pin must be looped back to the OSPI[x]_DQS input pin

• The signal propagation delay of the OSPI[x]_LBCLKO pin to the OSPI[x]_DQS pin (C to D) must be

approximately twice the propagation delay of the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device

CLK pin (A to B)

• The signal propagation delay of each OSPI[x]_D[y] and OSPI[x]_CSn[z] pin to the corresponding attached

OSPI/QSPI/SPI device data and control pin (E to F, or F to E) must be approximately equal to the signal

propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to B)

• 50 Ω PCB routing is recommended along with series terminations, as shown in Figure 9-2

• Propagation delays and matching:

– (C to D) = 2 x ((A to B) ± 30 ps), see the exception note below.

– (E to F, or F to E) = ((A to B) ± 60 ps)

Note

The External Board Loopback hold time requirement (defined by parameter number O16 in Table

7-101, OSPI0 Timing Requirements - PHY DDR Mode) may be larger than the hold time provided by

a typical OSPI/QSPI/SPI device. In this case, the propagation delay of OPSI[x]_LBCLKO pin to the

OSPI[x]_DQS pin (C to D) can be reduced to provide additional hold time.

OSPI[x]_CLK

OSPI/QSPI/SPI

Device Clock Input

OSPI/QSPI/SPI

Device IO[y], CS#

OSPI[x]_D[y],

OSPI[x]_CSn[z]

OSPI_Board_02

OSPI[x]_LBCLKO

OSPI[x]_DQS

OSPI Device DQS

* 0 Ω resistor (R1), located as close as possible to the OSPI[x]_CLK and OSPI[x]_LBCLKO pins, is a placeholder for fine tuning, if

needed.

Figure 9-2. OSPI Connectivity Schematic for External Board Loopback

AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

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