SPSB0813 datasheet(46/135 Pages) STMICROELECTRONICS

46 / 135 page

The RSTB bit is cleared after a read & clear of all the specific bits in the status registers, which caused the reset

event.

SPI error (SPIE)

The SPIE is a logical OR combination of errors related to a wrong SPI communication.

Physical layer error (PLE)

The PLE is a logical OR combination of errors related to the LIN and CAN FD transceivers.

Functional error (FE)

The FE is a logical OR combination of errors coming from functional blocks (for example, high-side over current).

Device error (DE)

The DE is a logical OR combination of errors related to device specific blocks (for example, VS over voltage, over

temperature.

Global warning (GW)

The GW is a logical OR combination of warning flags (for example, thermal warning).

Fail-safe (FS)

The FS bit indicates that the device was forced into a safe state due to mistreatment or fundamental internal

errors (for example, watchdog failure, voltage regulator failure).

4.2.2.7

Data-out payload

The payload (data bytes 1 to 3) is the data transferred from the slave device with every SPI communication to

the master device. The Payload always follows the OpCode and the address bits of the actual shifted in data

(In-frame-Response).

4.3

Address definition

Table 15. Device application access

Operating code

OC1

OC0

Table 16. RAM address range

RAM address

Description

Access

3FH

Configuration register

R/W

38H

Status register 8

R/C

…

32H

Status register 2

R/C

31H

Status register 1

R/C

…

22H

Control register 34

R/W

18H

Control register 24

R/W

…

02H

Control register 2

R/W

01H

Control register 1

R/W

00H

reserved

SPSB081

Address definition

DS14048 - Rev 1

page 46/135

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