SPSB0813 datasheet(77/135 Pages) STMICROELECTRONICS

77 / 135 page

Symbol

Parameter

Condition

Min

Typ

Max

Unit

Item

tdis DO L tri (1)

DO disable time

from low level to 3-

state

CL = 50 pF, Iload = 4

pull-up load to V1

100

B.029

ten DO tri H (1)

DO enable time

from tristate to high

level

CL = 50 pF, Iload = -1

pull-down load to

GND

100

B.030

td DO (1)

DO delay time

VDO < 0.3 V1 or

VDO > 0.7 V1,

CL = 50 pF

B.031

1. Guaranteed by design.

Table 60. CSN timing

Symbol

Parameter

Condition

Min Typ Max Unit

Item

tCSN_HI,min

Minimum CSN HI time,

active mode

Transfer of SPI-command to input register

0.5

μs

B.032

tCSNfail (1)

CSN low timeout

B.033

1. Guaranteed by design.

Figure 35. SPI – transfer timing diagram

The SPI can be driven by a microcontroller with its SPI peripheral running in the following mode:

CPOL = 0 and CPHA = 0.

For this mode input data is sampled by the low to high transition of the clock CLK, and output data is changed

from the high to low transition of CLK.

SPSB081

SPI

DS14048 - Rev 1

page 77/135

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