SPSB0813 datasheet(61/135 Pages) STMICROELECTRONICS

61 / 135 page

Table 36. Outputs OUT1–OUT4

Symbol

Parameter

Condition

Min

Typ

Max

Unit

Item

rON OUT1,2,3,4_25

on-resistance to supply

VS = 13. 5 V, Tamb=+25°C

IOUT1,2,3,4= -60mA

Ω

D.001

rON OUT1,2,3,4_125

VS = 13.5 V, Tamb=+125°C

IOUT1,2,3,4 = -60mA

Ω

D.002

IQLH_stdby

switched-off output current

high side drivers of OUT1-4 (1)

VOUT = 0 V, standby mode

-5

µA

D.003

IQLH_stdby_act

VOUT = 0 V, active mode

-10

µA

D.004

1. Negative value: leakages internally sink from driver output pin to internal IC ground positive value: Leakage sourced from

internal driver output pin to external ground.

5.10

Power outputs switching times

Table 37. Power outputs switching times

Symbol

Parameter

Condition

Min

Typ

Max

Unit

Item

td OFF H

Output delay time

high-side driver OFF

(OUT1,2,3,4) (delay

between CSN 50 % to

OUT at 20% of VS)

(figure 39)

VS= 13.5 V

V1= 5 V

Rload = 128 Ω

140

µs

D.005

td ON H

Output delay time

high-side driver ON

(OUT1,2,3,4) (delay

between CSN 50% to

OUT at 80% of VS)

(figure 39)

VS= 13.5 V

V1= 5 V

Rload = 128 Ω

µs

D.006

dVOUT/dt

Slew rate for drivers

OUT1…4

VS = 13.5 V(1)(2).

0.1

0.2

0.5

V/µs

D.007

fPWM1

PWM switching

frequency

VS /VSREG = 13.5 V; tested

by scan

125

D.008

fPWM2

PWM switching

frequency

VS /VSREG = 13.5 V; tested

by scan

250

D.009

SPI configurable duty

cycle for OUT1…4

0.1% steps; tested by scan

0.1

100

D.010

1. Rload = 128 Ω at OUT1,2,3 ,4, in high on-resistance mode.

2. Slope dVOUT/dt is measured between 20% and 80% of the final output voltage value

SPSB081

Power outputs switching times

DS14048 - Rev 1

page 61/135

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