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SPSB0813 数据表(PDF) 47 Page - STMicroelectronics |
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SPSB0813 数据表(HTML) 47 Page - STMicroelectronics |
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47 / 135 page ![]() Table 17. Device information read access Operating code OC1 OC0 1 1 Table 18. ROM address range ROM address Description Access 3FH <Advanced Op.> W 3EH <GSB options> R … 20H <SPI CPHA test> R 16H <WD bit pos. 4> R 15H <WD bit pos. 3> R 14H <WD bit pos. 2> R 13H <WD bit pos. 1> R 12H <WD type 2> R 11H <WD type 1> R 10H <SPI mode> R … 0AH <silicon Ver.> R … 05H <device No.4> R 04H <device No.3> R 03H <device No.2> R 02H <device No.1> R 01H <device family> R 00H <company code> R 4.3.1 Information registers The device information registers can be read by using OpCode ‘11’. After shifting out the GSB the 8-bit wide payload is transmitted. By reading device information registers a communication width, which is minimum 16 bits plus a multiple by 8 can be used. After shifting out the GSB followed by the 8-bit wide payload a series of ‘0’ is shifted out at the SDO. Table 19. SPSB081 information registers map ROM address Description Access Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3FH <Advanced Op.> 3EH <GSB options> R → 0 0 0 0 0 0 0 0 … 20H <SPI CPHA test> R → 0 1 0 1 0 1 0 1 16H <WD bit pos. 4> R → C0H 15H <WD bit pos. 3> R → 7FH 14H <WD bit pos. 2> R → C0H 13H <WD bit pos. 1> R → 41H SPSB081 Address definition DS14048 - Rev 1 page 47/135 |
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