SPSB0813 datasheet(20/135 Pages) STMICROELECTRONICS

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Figure 10. Main operating modes

3.6

Configurable window watchdog

During normal operation, the watchdog monitors the microcontroller within a programmable trigger cycle.

After power-on or standby mode, the watchdog starts with a timeout (long open window tLW). The timeout allows

the microcontroller to run its own setup and then to start the window watchdog by setting TRIG=1. Later, the

microcontroller has to serve the watchdog by alternating the watchdog trigger bit within the safe trigger area Tswx.

The trigger time is configurable by SPI.

A correct watchdog trigger signal will immediately start the next cycle.

After eight watchdog failures in sequence, the V1 regulator is switched off for tv1off. After seven additional

watchdog failures the V1 regulator is turned off permanently and the device is forced into VBAT_standby mode.

The status bit FORCED_SLEEP_WD (SR1) is set. A wake-up is possible by any activated wake-up source.

In case of a watchdog failure, the power outputs and V2 are switched off and the device enters fail-safe mode. All

control registers are set to their fail-safe values.

The following diagrams illustrate the watchdog behavior of the device. The diagrams are split into 3 parts. The

first diagram shows the functional behavior of the watchdog without any error. The second diagram covers the

behavior covering all the error conditions, which can affect the watchdog behavior. The third diagram shows the

transition in and out of debug mode. All three diagrams can be overlapped to get all the possible state transitions

under all circumstances. For a better readability, they were split in normal operating, operating with errors and

debug mode.

SPSB081

Configurable window watchdog

DS14048 - Rev 1

page 20/135

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