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SPSB0813 数据表(PDF) 76 Page - STMicroelectronics |
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SPSB0813 数据表(HTML) 76 Page - STMicroelectronics |
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76 / 135 page  Symbol Parameter Condition Min Typ Max Unit Item fCLK SPI input frequency at CLK Tested by scan 10 MHz B.012 1. Value of input capacity is not measured in production test. Parameter guaranteed by design. Table 57. DI, CLK and CSN timing Symbol Parameter Condition Min Typ Max Unit Item tCLK clock period V1 = 5 V; tested by scan 100 ns B.013 tCLKH clock high time V1 = 5 V 40 ns B.014 tCLKL clock low time V1 = 5 V 40 ns B.015 tset CSN CSN setup time, CSN low before rising edge of CLK V1 = 5 V 150 ns B.016 tset CLK CLK setup time, CLK high before rising edge of CSN V1 = 5 V 150 ns B.017 tset DI DI setup time V1 = 5 V 25 ns B.018 thold DI DI hold time V1 = 5 V 25 ns B.019 tr in rise time of input signal DI, CLK, CSN V1 = 5 V(1) 25 ns B.020 tf in fall time of input signal DI, CLK, CSN V1 = 5 V (1) 25 ns B.021 1. Guaranteed by design. Table 58. Output: DO Symbol Parameter Condition Min Typ Max Unit Item VDOL output low level V1 = 5 V, IDO = -4mA 0.5 V B.022 VDOH output high level V1 = 5 V, IDO = 4 mA V1-0.5 V B.023 IDOLK tristate leakage current VCSN = V1, 0V < VDO <´V1 -10 10 μA B.024 CDO (1) tristate input capacitance VCSN = V1, 0 V < V1 < 5.3 V 10 15 pF B.025 1. Guaranteed by design. Table 59. DO timing Symbol Parameter Condition Min Typ Max Unit Item tr DO DO rise time CL = 50 pF, Iload = -1 mA 25 ns B.026 tf DO (1) DO fall time CL = 50 pF, Iload = 1 mA 25 ns B.027 ten DO tri L(1) DO enable time from tristate to low level CL = 50 pF, Iload = 1 mA pull-up load to V1 50 100 ns B.028 SPSB081 SPI DS14048 - Rev 1 page 76/135 |
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