SPSB0813 datasheet(116/135 Pages) STMICROELECTRONICS

116 / 135 page

Bit

Name

Description

‘1’ = wake-up

Bits are latched until a “Read and clear” command

WU1 WAKE

WAKE CAN

WAKE LIN

WAKE TIMER

DEBUG _ACTIVE

Indicates device is in debug mode

‘1’ = debug mode

Bit is latched until a “Read and clear” command

V1UV

Indicates undervoltage condition at voltage regulator V1 (V1 < VRTx)

‘1’ = undervoltage

Bit is latched until a “Read and clear” command

V1_RESTART_2

Indicates that the number of TSD2 events that caused a restart of voltage regulator V1

Bits cannot be cleared; the counter is automatically cleared if no additional TSD2 event occurs within 1

minute.

V1_ RESTART_1

V1_ RESTART_0

WDFAIL_CNT_3

Indicates number of subsequent watchdog failures.

Bits cannot be cleared; they are cleared with a valid watchdog trigger

WDFAIL_CNT_2

WDFAIL_CNT_1

WDFAIL_CNT_0

DEVICE_STATE_1

0 0: Active mode after power-on, or after read&clear command

0 1: Active mode after wake-up from V_standby mode (before read&clear command)

1 0: Active mode after wake-up from VBAT_standby mode (before read&clear command)

1 1: Not used

Bit is latched until a read&clear command

After a “read and clear access”, the device state is updated

DEVICE_STATE_0

TSD2

Thermal shutdown 2 was reached

Bit is latched until a “Read and clear” command for Cluster 4 (bit 22 in SR7)

TSD1

Thermal shutdown 1 was reached

Bit is latched until a “Read and clear” command for all Clusters (bit 16-23 in SR7)

FORCED_SLEEP_TS

D2/V1SC

Device entered forced sleep mode due to:

•

Thermal shutdown or

•

Short circuit on V1 during startup

Bit is latched until a read&clear command

FORCED_SLEEP_W

Device entered forced sleep mode due to multiple watchdog failures

Bit is latched until a read&clear command

WDFAIL

Watchdog failure

Bit is latched until a “Read and clear” command

VPOR

VREG Power-on Reset threshold (VPOR)(1) reached

Bit is latched until a “Read and clear” command

1. If VPOR is set after a cold startup, the device comes from a Power-on Reset.

SPSB081

Status registers

DS14048 - Rev 1

page 116/135

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