VL6180 datasheet(14/73 Pages) STMICROELECTRONICS

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Functional description

VL6180

14/73

DocID024986 Rev 14

2.3

Timing diagram

Figure 8 and Table 4.show the VL6180 power-up timing constraints.



AVDD_VCSEL must be applied before or at the same time as AVDD.



GPIO0 defaults to an active low shutdown input. When GPIO0 = 0, the device is in

hardware standby. If GPIO0 is not used it should be connected to AVDD.



The internal microprocessor (MCU) boot sequence commences when AVDD is up and

GPIO0 is high whichever is the later.



GPIO1 power-up default is output low. It is tri-stated during the MCU boot sequence.

Note:

In hardware standby, GPIO1 is output low and will sink current through any pull-up resistor.

This leakage can be minimized by increasing the value of the pull-up resistor.



After the MCU boot sequence the device enters software standby. Host initialization

can commence immediately after entering software standby.

Figure 8. Power-up timing

Table 4. Power-up timing constraints

Symbol

Parameter

Min

Max

Unit

AVDD_VCSEL power applied after AVDD

Minimum reset on GPIO0

100

GPIO1 output low after hardware standby

400

s

MCU boot

Software standby to host initialization

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