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VL6180 数据表(PDF) 39 Page - STMicroelectronics |
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VL6180 数据表(HTML) 39 Page - STMicroelectronics |
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39 / 73 page ![]() DocID024986 Rev 14 39/73 VL6180 Device registers 69 6 Device registers This section describes in detail all user accessible device registers. Registers are grouped by function as shown in Table 22. to make them easier to read but also to simplify multi-byte read/write I2C accesses (burst mode). More details in Section 4. Reset values are given for each register which denotes the register value in software standby. Note that registers can be 8-,16- or 32-bit. Multi-byte registers are always addressed in ascending order with MSB first as shown in Table 23. 6.1 Register encoding formats Some registers are encoded to allow rational numbers to be expressed efficiently. Table 24 gives an explanation of 9.7 and 4.4 encoding formats. Table 25 gives a summary of the device registers. Table 22. Register groups Register group Address range IDENTIFICATION 0x000 - 0x00F SYSTEM SETUP 0x010 - 0x017 RANGE SETUP 0x018 - 0x037 RESULTS 0x04D - 0x080 Table 23. 32-bit register example Register address Byte Address MSB Address + 1 .. Address + 2 .. Address + 3 LSB Table 24. Register formats Format Description 9.7 9 integer bits + 7 fractional bits (stored over 2 bytes) For example, the value 4.2 is multiplied by 128, rounded and stored as 537 decimal. To decode, divide 537 by 128 = 4.19. |
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