ADF4377 datasheet(39/79 Pages) AD

39 / 79 page

Data Sheet

ADF4377

APPLICATIONS INFORMATION

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Rev. 0 | 39 of 79

Table 35. Manually Programmed VCO Calibration Settings

Bit Fields

Value

M_VCO_CORE

Program M_VCO_CORE,

M_VCO_BAND, and M_VCO_BIAS with

recorded VCO_CORE, VCO_BAND,

and VCO_BIAS values, respectively,

from the Standard Power-Up and

Initialization Sequence, Automatic VCO

Calibration section

M_VCO_BAND

M_VCO_BIAS

ALIGNING MULTIPLE ADF4377 OUTPUT

PHASES

Aligning multiple ADF4377 output phases can be broken into two

steps. The first step ensures that the reference dividers, reference

doubler, and clock output divider of the multiple devices are setup

correctly to ensure phase alignment. The second step minimizes

output to output skew between multiple ADF4377 devices.

Step 1: Phase Alignment

The ADF4377 architecture includes the clock output divider and the

output invert inside the integer PLL feedback loop (see Figure 1),

which allows the locked PLL to align the clock output divider phase

to the reference input phase. Therefore, to align multiple ADF4377

output phases, ensure that the reference phases are aligned at all

the reference input pins of the ADF4377.

Because the reference divider and reference doubler are outside

of the PLL loop, refer to Table 36 to ensure that phase alignment

between multiple ADF4377 devices is guaranteed.

Table 36. Reference Settings to Align Multiple ADF4377 Devices

Reference Divider and Doubler State

Guaranteed Reference to Output

Phase Alignment

EN_RDBLR = 1

Yes

R_DIV = 1

Yes

R_DIV > 1

When fOUT/fREF = integer, and fREF ≤

fOUT

Step 2: Output to Output Skew Adjustment

Any variation in reference input to output propagation delay (tPD)

between multiple ADF4377 devices presents itself as output skew

between multiple ADF4377 devices.

To minimize tPD across process and temperature, select the DMA

of the reference input buffer by setting REF_SEL = 0. When the

DMA is selected, the typical tPD standard deviation due to process

variation is 3 ps with a temperature coefficient (tPD-TC) of 0.03

ps/°C, as shown in Figure 24 and Figure 20, respectively.

Due to the controlled tPD of the ADF4377 devices, it is reasona-

ble to expect that a significant portion of the total system skew

(tSKEW_SYSTEM) is due to propagation delay mismatches in traces or

cables (tSKEW_B, tSKEW_D), and skew in other components (tSKEW_A)

or instruments (tMEAS_ERROR, tCHAN1, and tCHAN2). Figure 90 and

Equation 24 provide several sources of possible output skew error

in a typical system. The Analog Dialogue article, "Clock Skew in

Large Multi-GHz Clock Trees" (Volume 53, January 2019), outlines

the skew trade-offs in component selection, board design, and

end-user cost requirements in large clock trees.

Figure 90. Total System Skew

tSKEW_SYSTEM=tSKEW_A+tSKEW_B+tSKEW_C

+tSKEW_D+tMEAS_ERROR

(24)

where:

tSKEW_A = tA1 − tA0

tSKEW_B = tPD_B1 − tPD_B0

tSKEW_C = tPD_C1 − tPD_C0

tSKEW_D = tPD_D1 − tPD_D0

tMEAS_ERROR = tCHAN1 − tCHAN2

To further minimize clock skew between multiple clocks, the

ADF4377 devices provide SPI programmable adjustments to in-

crease or decrease the tPD in sub-ps steps. Table 37 and Table

38 provide a comparison of the multiple reference to output delay

controls. In large clock trees, these tPD adjustments can alleviate

output to output skew trade-offs in component selection, board

design, and end-user cost requirements.

Table 37. ADF4377 Reference to Output Delay Control Comparison

Parameter

Referenc

e Delay

Feedback

Delay

Charge Pump Bleed

Current

Output Invert

Bits

R_DEL

N_DEL

EN_BLEED, BLEED_I

bit fields, Bits[9:0],

BLEED_POL

INV_CLKOUT

tPD

Increases Decrease

BLEED_POL = 0,

increases

Inverts output,

see Table 19

BLEED_POL = 1,

decreases

Number of

Steps

127

1023

Step Size

~1 ps

~0.01 ps to 65 ps,

varies with CP_I and

fPFD Equation 9

1 2×fOUT

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