Data Sheet

ADF4377

APPLICATIONS INFORMATION

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Rev. 0 | 42 of 79

Design Considerations

The Reference and SYSREF Distribution Selection section, Board

Layout Considerations section, Skew Adjustment Options section,

Skew Measurement, Adjustments and System Error section, and

Power-Up, Programming, and Measurement Sequence section pro-

vide an overview of several design considerations when designing

a low clock skew system with multiple ADF4377 devices and

multiple JESD204B/C converters that include a TDC.

Reference and SYSREF Distribution Selection

In high performance applications that require minimum clock skew

and drift, it is recommended to choose a reference distribution de-

vice whose additive noise floor meets the requirements described

in the Reference Source Considerations section, and whose output

slew rate allows for the DMA option of the ADF4377 reference input

buffer (see Table 7). The DMA option minimizes tPD-TC, as shown

in Figure 20. Most reference distribution ICs output a square wave.

The slew rate of a square wave is determined by Equation 25.

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(25)

The HMC7044, HMC7043, LTC6952, LTC6953, LTC6955,

LTC6954, or LTC6957-1 are adequate reference distribution ICs

for the noise floor and rise time requirements.

By using multiple outputs from a single reference and SYSREF

distribution IC, the reference and SYSREF temperature delay drift

match. See the LTC6952, LTC6953, and LTC6957-1 data sheets for

more information on output skew variation over process per output

to aid in SYSREF output selection. Choosing the outputs with the

least skew for SYSREF outputs improves the skew adjustment

errors, as described in the Skew Measurement, Adjustments and

System Error section.

Selecting a JESD204B/C reference and SYSREF distribution IC

requires knowledge of the AD9213 JESD204B serial lane rates and

the clock and SYSREF requirements of the field programmable

gate array (FPGA). Both these topics are beyond the scope of this

data sheet. However, ADI has created several JESD204B/C devel-

opment platforms that provide hardware and software examples

that can aid further in the reference and SYSREF distribution IC

selection. Several of these platforms are available on the Analog

Devices website.

Board Layout Considerations

During hardware design, it is best to match the electrical lengths (ℓ)

for the reference, clock, and SYSREF traces in Figure 92, as shown

in Table 40.

Table 40. Trace Length Matching for Skew Optimization

If Skew Adjustments

Performed

Skew Optimization

Skew Temperature Coef-

ficient Optimization

No

ℓREFA = ℓREFB, ℓCLKA =

ℓCLKB, and ℓSYSREFA =

ℓSYSREFB

ℓSYSREFx = ℓREFx + ℓCLKx

Yes

ℓSYSREFA = ℓSYSREFB

ℓSYSREFx = ℓREFx + ℓCLKx

Refer to the Analog Dialogue article, "Clock Skew in Large Multi-

GHz Clock Trees" (Volume 53, January 2019) for more information

on PCB material selection, transmission line selection, cable selec-

tion, and several other concerns related to clock skew.

Signal attenuation is proportional to the length of the trace and

signal frequency. Converter clock traces must be treated as RF

traces because any unwanted spurious or noise that couples onto

the clock signals can affect the performance of the converters.

Therefore, it is recommended to minimize the ℓCLKA and ℓCLKB trace

lengths to optimize performance and limit attenuation. Refer to the

ADC Clock and Jitter Considerations section for additional informa-

tion on clock performance concerns, routing, and recommended

schematics.

In most cases, trace matching board layout errors can be corrected

with the ∆t functions in the reference and SYSREF distribution IC,

the ADF4377 or the AD9213, shown in Figure 92.

Skew Adjustment Options

Figure 92 has skew adjustment (∆t) blocks in the Stage 1 IC, the

ADF4377, and the AD9213. In most cases, the ADF4377 is the pre-

ferred skew adjustment option in terms of maximizing performance.

The ADF4377 ∆t blocks are discussed in Table 37. For this design

example, either R_DEL and N_DEL or BLEED_I bit fields, Bits[9:0]

are valid options. However, in Figure 92, only R_DEL and N_DEL

are shown.

The AD9213 also provides a ∆t block capable of sub-ps step sizes.

Like any ∆t block, there is an opportunity for increased phase noise.

The ADF4377 and AD9213 ∆t blocks affect phase noise at different

frequency offsets, as shown in Table 41.

Table 41. Clock Phase Noise Region Affected by ADF4377 and AD9213 Δt

Blocks

Δt Block

In-Band Phase Noise

Wideband Phase Noise

< ADF4377 Loop Filter

Bandwidth

~10 MHz to fCLK

ADF4377 ∆t

Minimal additive noise,

refer to Table 38

None

AD9213 ∆t

None

Minimal additive noise

The reference and SYSREF distribution IC in Figure 92 has a ∆t

block for each output. The typical Stage 1 IC skew adjustment

step size is in the 11 ps (LTC6952, LTC6953) to 25 ps (HMC7044,

HMC7043) range. These ∆t blocks typically increase the phase