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Data Sheet

ADF4377

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 11 of 79

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

SDIO

Serial Data Input/Output. 1.8 V and 3.3 V programmable CMOS input/output. When configured as an input, the serial port uses this CMOS

input for data. In 3-wire readback mode (default mode), this pin outputs data from the serial port during a read communication burst.

SCLK

Serial Port Clock. 1.8 V and 3.3 V compatible. This CMOS input clocks serial port input data on its rising edge.

SDO

Optional Serial Data Output. 1.8 V and 3.3 V programmable CMOS output. In 3-wire mode (default mode), this three state CMOS pin

remains in a high impedance state. In 4-wire readback mode, this pin presents data from the serial port during a read communication

burst. When the CS is deasserted, SDO returns to a high impedance. Optionally, attach a resistor of > 200 kΩ to prevent a floating output.

V3_LDO

3.15 V to 3.45 V Positive Power Supply Pin for the Internal LDO Circuitry. Short this pin to the other pins in 3.3 V Power Supply Group 1.

MUXOUT

Internal Device Mux Output. This output pin can be connected to multiple internal nodes for factory test and debug purposes.

38, 39

No Connect or GND. These pins are connected internally to ESD diodes.

V3_IN

3.15 V to 3.45 V Positive Power Supply. Short this pin to the other pins in 3.3 V Power Supply Group 1.

42, 43

REFP, REFN

Reference Input Signal. This differential input is buffered with a delay matched amplifier (DMA) for well controlled reference to output

propagation delays (default mode, REF_SEL = 0). For low slew rate reference input signals, an alternate low noise amplifier (LNA) can

be selected via the serial port (REF_SEL = 1). Reference inputs are self-biased and must be ac-coupled with 1 μF capacitors. Reference

inputs accept differential or single-ended inputs.

V3_REF

3.15 V to 3.45 V Positive Power Supply Pin for the PLL Reference Circuitry. Short this pin to the other pins in 3.3 V Power Supply Group 1.

V3_PFD

3.15 V to 3.45 V Positive Power Supply Pin for PFD Circuitry. Short this pin to the other pins in 3.3 V Power Supply Group 1.

V5_CP

4.75 V to 5.25 V Positive Power Supply Pin for Charge Pump Circuitry. This pin must be isolated from the V5_VCO supply plane.

Charge Pump Output. This bidirectional current output is normally connected to the external loop filter.

Exposed Pad

Exposed Pad. Negative power supply (ground). The exposed pad must be soldered directly to the PCB land. The PCB land pattern must

have multiple thermal vias to the ground plane for both low ground inductance and low thermal resistance.

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