ADF4377 datasheet(7/79 Pages) AD

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Data Sheet

ADF4377

SPECIFICATIONS

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Rev. 0 | 7 of 79

Table 1.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

TEMPERATURE SENSOR (ADC)

ADC Clock Frequency

fADC_CLK

400

kHz

ADC clock divider output

ADC Clock Divider Frequency

fADC_CLKDIV

125

MHz

ADC clock divider input

Resolution

Bits

1 1.2 V < VCP < 3.4 V.

2 Valid for 1.60 V ≤ VVTUNE ≤ 2.85 V with device calibrated after a power cycle or software power-on reset.

3 Based on characterization.

4 Device setup: fREF = 200 MHz, fPFD = 200 MHz, fOUT = 3000 MHz, ENCLK1 = ENCLK2 = CE = HIGH. Bit fields: R_DEL= 0, N_DEL = 0, CP_I = 15, CLKOUT1_OP = 1,

CLKOUT2_OP = 1, REF_SEL = 0, EN_BLEED = 0, PD_RDET = 0, PD_ADC = 0, PD_LD = 0, LOCKED = 1.

5 Device Setup: fREF = 100 MHz, fPFD = 200 MHz, fOUT = 12.8 GHz, ENCLK1 = ENCLK2 = CE = HIGH. Bit fields: R_DEL= 0, N_DEL = 0, CP_I = 15, CLKOUT1_OP = 1,

CLKOUT2_OP = 1, REF_SEL = 0, EN_BLEED = 0, PD_RDET = 0, PD_ADC = 0, PD_LD = 0, LOCKED = 1, EN_DNCLK = EN_DRCLK = EN_ADC_CLK = 0.

6 Device Setup: fREF = 1000 MHz, fPFD = 500 MHz, ENCLK1 = ENCLK2 = CE = HIGH. Bit fields: R_DEL = 0, N_DEL_0, CP_I = 15, CLKOUT1_OP = 1, CLKOUT2_OP = 1,

REF_SEL = 0, EN_BLEED = 0, PD_RDET = 0, PD_ADC = 0, PD_LD = 0, LOCKED = 1, the reference oscillator is the 0-CEGM-058AWEL-R-1GHz from NEL Frequency

Control.

7 Phase integration range 1 kHz to fOUT produces the same result as when clocking an ADC.

8 Refer to Equation 18 through Equation 22. These values are modeled in ADIsimPLL

™.

SERIAL INTERFACE TIMING CHARACTERISTICS

V3.3V_1 = V3.3V_2 = 3.15 V to 3.45 V, VV5_VCO = VV5_CP = VV5_CAL = 4.75 V to 5.25 V, all voltages are with respect to GND, TA = −40°C to

+105°C, operating temperature range, unless otherwise noted.

Table 2.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

SERIAL INTERFACE (CSB, SCLK, SDIO, SDO)

See Figure 2, Figure 3, and Figure 4

SCLK Frequency

fSCLK

MHz

fSCLK = 1/tSCLK

SCLK Pulse Width High

tHIGH

7.6

SCLK Pulse Width Low

tLOW

7.6

SDIO Setup Time

tDS

SDIO Hold Time

tDH

SCLK Fall Edge to SDIO Valid Prop Delay

tACCESS_SDIO

7.6

SCLK Fall Edge to SDO Valid Prop Delay

tACCESS_SDO

7.6

CSB Rising Edge to SDIO High-Z

7.6

CSB Falling Edge to SCLK Rise Setup Time

SCLK Rising Edge to CSB Rise Hold Time

Timing Diagrams

Figure 2. Write Timing Diagram

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