MPC8540 datasheet(21/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

xxi

Contents

Paragraph

Number

Title

Page

Number

13.4.3.9

SDRAM Read/Write Transactions....................................................................... 13-60

13.4.3.10

SDRAM MODE-SET Command Timing............................................................ 13-60

13.4.3.11

SDRAM Refresh.................................................................................................. 13-61

13.4.3.11.1

SDRAM Refresh Timing ................................................................................. 13-61

13.4.4

User-Programmable Machines (UPMs)................................................................... 13-62

13.4.4.1

UPM Requests ..................................................................................................... 13-63

13.4.4.1.1

Memory Access Requests................................................................................ 13-64

13.4.4.1.2

UPM Refresh Timer Requests ......................................................................... 13-65

13.4.4.1.3

Software Requests—RUN Command ............................................................. 13-65

13.4.4.1.4

Exception Requests.......................................................................................... 13-66

13.4.4.2

Programming the UPMs ...................................................................................... 13-66

13.4.4.3

UPM Signal Timing............................................................................................. 13-66

13.4.4.4

RAM Array .......................................................................................................... 13-67

13.4.4.4.1

RAM Words..................................................................................................... 13-68

13.4.4.4.2

Chip-Select Signal Timing (CSTn) ................................................................. 13-72

13.4.4.4.3

Byte Select Signal Timing (BSTn) .................................................................. 13-72

13.4.4.4.4

General-Purpose Signals (GnTn, GOn)........................................................... 13-73

13.4.4.4.5

Loop Control (LOOP) ..................................................................................... 13-73

13.4.4.4.6

Repeat Execution of Current RAM Word (REDO) ......................................... 13-74

13.4.4.4.7

Address Multiplexing (AMX) ......................................................................... 13-74

13.4.4.4.8

Data Valid and Data Sample Control (UTA) ................................................... 13-75

13.4.4.4.9

LGPL[0:5] Signal Negation (LAST) ............................................................... 13-76

13.4.4.4.10

Wait Mechanism (WAEN) ............................................................................... 13-76

13.4.4.5

Synchronous Sampling of LUPWAIT for Early Transfer Acknowledge ............ 13-77

13.4.4.6

Extended Hold Time on Read Accesses .............................................................. 13-77

13.4.4.7

Memory System Interface Example Using UPM ................................................ 13-78

13.5

Initialization/Application Information ......................................................................... 13-84

13.5.1

Interfacing to Peripherals......................................................................................... 13-84

13.5.1.1

Multiplexed Address/Data Bus and Unmultiplexed Address Signals ................. 13-84

13.5.1.2

Peripheral Hierarchy on the Local Bus................................................................ 13-84

13.5.1.3

Peripheral Hierarchy on the Local Bus for Very High Bus Speeds ..................... 13-85

13.5.1.4

GPCM Timings.................................................................................................... 13-86

13.5.2

Bus Turnaround ....................................................................................................... 13-87

13.5.2.1

Address Phase After Previous Read .................................................................... 13-87

13.5.2.2

Read Data Phase After Address Phase ................................................................ 13-88

13.5.2.3

Read-Modify-Write Cycle for Parity Protected Memory Banks ......................... 13-88

13.5.2.4

UPM Cycles with Additional Address Phases..................................................... 13-88

13.5.3

Interface to Different Port-Size Devices.................................................................. 13-88

13.5.4

Interfacing to SDRAM............................................................................................. 13-90

13.5.4.1

Basic SDRAM Capabilities of the Local Bus...................................................... 13-90

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