MPC8540 datasheet(39/1302 Pages) FREESCALE

39 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

xxxix

Contents

Paragraph

Number

Title

Page

Number

20.3.1.2

Watchpoint Monitor Address Register (WMAR)................................................ 20-13

20.3.1.3

Watchpoint Monitor Address Mask Register (WMAMR) ................................. 20-14

20.3.1.4

Watchpoint Monitor Transaction Mask Register (WMTMR) ............................. 20-14

20.3.1.5

Watchpoint Monitor Status Register (WMSR).................................................... 20-16

20.3.2

Trace Buffer Register Descriptions.......................................................................... 20-16

20.3.2.1

Trace Buffer Control Registers (TBCR0, TBCR1) ............................................. 20-16

20.3.2.2

Trace Buffer Address Register (TBAR) .............................................................. 20-19

20.3.2.3

Trace Buffer Address Mask Register (TBAMR)................................................. 20-19

20.3.2.4

Trace Buffer Transaction Mask Register (TBTMR)............................................ 20-20

20.3.2.5

Trace Buffer Status Register (TBSR) .................................................................. 20-21

20.3.2.6

Trace Buffer Access Control Register (TBACR) ................................................ 20-22

20.3.2.7

Trace Buffer Access Data High Register (TBADHR)......................................... 20-22

20.3.2.8

Trace Buffer Access Data Register (TBADR)..................................................... 20-23

20.3.3

Context ID Registers................................................................................................ 20-24

20.3.3.1

Programmed Context ID Register (PCIDR) ........................................................ 20-24

20.3.3.2

Current Context ID Register (CCIDR) ................................................................ 20-24

20.3.4

Trigger Out Function ............................................................................................... 20-25

20.3.4.1

Trigger Out Source Register (TOSR) .................................................................. 20-25

20.4

Functional Description................................................................................................. 20-26

20.4.1

Source and Target ID ............................................................................................... 20-26

20.4.2

PCI/PCI-X Interface Debug..................................................................................... 20-27

20.4.3

DDR SDRAM Interface Debug ............................................................................... 20-28

20.4.3.1

Debug Information on Debug Pins ...................................................................... 20-28

20.4.3.2

Debug Information on ECC Pins ......................................................................... 20-28

20.4.4

Local Bus Interface Debug ...................................................................................... 20-28

20.4.5

Watchpoint Monitor ................................................................................................. 20-28

20.4.5.1

Watchpoint Monitor Performance Monitor Events ............................................. 20-29

20.4.6

Trace Buffer ............................................................................................................. 20-29

20.4.6.1

Traced Data Formats (as a Function of TBCR1[IFSEL]).................................... 20-30

20.5

Initialization ................................................................................................................. 20-33

Chapter 21

10/100 Fast Ethernet Controller

21.1

Introduction.................................................................................................................... 21-1

21.1.1

10/100 Fast Ethernet Controller Overview................................................................ 21-5

21.2

Features .......................................................................................................................... 21-6

21.3

Modes of Operation ....................................................................................................... 21-7

21.4

External Signal Descriptions ......................................................................................... 21-7

21.4.1

Detailed Signal Descriptions ..................................................................................... 21-8

MPC8540 数据表(PDF) 39 Page - Freescale Semiconductor, Inc

MPC8540 数据表(HTML) 39 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载