MPC8540 datasheet(49/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

xlix

Figures

Figure

Number

Title

Page

Number

13-9

UPM Data Register (MDR) ................................................................................................ 13-22

13-10

SDRAM Machine Mode Register (LSDMR) ..................................................................... 13-22

13-11

UPM Refresh Timer (LURT) .............................................................................................. 13-24

13-12

LSRT SDRAM Refresh Timer (LSRT)............................................................................... 13-25

13-13

Transfer Error Status Register (LTESR) ............................................................................. 13-26

13-14

Transfer Error Check Disable Register (LTEDR) ............................................................... 13-27

13-15

Transfer Error Interrupt Enable Register (LTEIR).............................................................. 13-28

13-16

Transfer Error Attributes Register (LTEATR) .................................................................... 13-29

13-17

Transfer Error Address Register (LTEAR) ......................................................................... 13-30

13-18

Local Bus Configuration Register....................................................................................... 13-31

13-19

Clock Ratio Register (LCRR) ............................................................................................. 13-32

13-20

Basic Operation of Memory Controllers in the LBC .......................................................... 13-34

13-21

Example of 8-Bit GPCM Writing 32 Bytes to Address 0x5420 ......................................... 13-36

13-22

Basic LBC Bus Cycle with LALE, TA, and LCSn ............................................................. 13-37

13-23

Local Bus to GPCM Device Interface ................................................................................ 13-39

13-24

GPCM Basic Read Timing (XACS = 0, ACS = 1x, TRLX = 0,

CLKDIV = 4,8) .............................................................................................................. 13-39

13-25

GPCM Basic Write Timing (XACS = 0, ACS = 00, CSNT = 1, SCY = 1,

TRLX = 0, CLKDIV = 4 or 8) ....................................................................................... 13-45

13-26

GPCM Relaxed Timing Read (XACS = 0, ACS = 1x, SCY = 1, CSNT = 0,

TRLX = 1, CLKDIV = 4 or 8) ....................................................................................... 13-46

13-27

GPCM Relaxed Timing Back-to-Back Writes (XACS = 0, ACS = 1x,

SCY = 0, CSNT = 0, TRLX = 1, CLKDIV = 4 or 8)..................................................... 13-46

13-28

GPCM Relaxed Timing Write (XACS = 0, ACS = 10, SCY = 0, CSNT = 1,

TRLX = 1, CLKDIV = 4 or 8) ....................................................................................... 13-47

13-29

GPCM Relaxed Timing Write (XACS = 0, ACS = 00, SCY = 1, CSNT = 1,

TRLX = 1, CLKDIV = 4 or 8) ....................................................................................... 13-48

13-30

GPCM Read Followed by Read (TRLX = 0, EHTR = 0, Fastest Timing) ......................... 13-49

13-31

GPCM Read Followed by Write (TRLX = 0, EHTR = 1, 1-Cycle Extended

Hold Time on Reads) ..................................................................................................... 13-49

13-32

External Termination of GPCM Access.............................................................................. 13-50

13-33

Connection to a 32-Bit SDRAM with 12 Address Lines.................................................... 13-52

13-34

SDRAM Address Multiplexing .......................................................................................... 13-54

13-35

PRETOACT = 2 (2 Clock Cycles)...................................................................................... 13-55

13-36

ACTTORW = 2 (2 Clock Cycles)....................................................................................... 13-56

13-37

CL = 2 (2 Clock Cycles) ..................................................................................................... 13-56

13-38

WRC = 2 (2 Clock Cycles) ................................................................................................. 13-57

13-39

RFRC = 4 (6 Clock Cycles) ................................................................................................ 13-57

13-40

BUFCMD = 1, LCRR[BUFCMDC] = 2............................................................................. 13-58

13-41

SDRAM Single-Beat Read, Page Closed, CL = 3 .............................................................. 13-58

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