MPC8540 datasheet(84/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

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Freescale Semiconductor

Part II, “e500 Core Complex and L2 Cache,” describes the many features of the MPC8540 core

processor at an overview level and the interaction between the core complex and the L2 cache. The

following chapters are included:

•

Chapter 5, “Core Complex Overview,” provides an overview of the e500 core processor

and the L1 caches and MMU that, together with the core, comprise the core complex.

•

Chapter 6, “Core Register Summary,” provides a listing of the e500 registers in reference

form.

•

Chapter 7, “L2 Look-Aside Cache/SRAM,” describes the L2 cache of the MPC8540. Note

that the L2 cache can also be addressed directly as memory-mapped SRAM.

Part III, “Memory and I/O Interfaces,” defines the memory and I/O interfaces of the MPC8540 and

how these blocks interact with one another and with other blocks on the device. The following

chapters are included:

•

Chapter 8, “e500 Coherency Module,” defines the e500 coherency module and how it

facilitates communication between the e500 core complex, the L2 cache, and the other

blocks that comprise the coherent memory domain of the MPC8540.

The ECM provides a mechanism for I/O-initiated transactions to snoop the core complex

bus (CCB) of the e500 core in order to maintain coherency across cacheable local memory.

It also provides a flexible, easily expandable switch-type structure for e500- and

I/O-initiated transactions to be routed (dispatched) to target modules on the MPC8540.

•

Chapter 9, “DDR Memory Controller,” describes the DDR SDRAM memory controller of

the MPC8540. This fully programmable controller supports most DDR memories available

today, including both buffered and unbuffered devices. The built-in error checking and

correction (ECC) ensures very low bit-error rates for reliable high-frequency operation.

Dynamic power management and auto-precharge modes simplify memory system design.

A large set of special features like DLL software override, crawl mode, and ECC error

injection support rapid system debug.

•

Chapter 10, “Programmable Interrupt Controller,” describes the embedded programmable

interrupt controller (PIC) of the MPC8540. This controller is an OpenPIC-compliant

interrupt controller that provides interrupt management, and is responsible for receiving

hardware-generated interrupts from different sources (both internal and external),

prioritizing them and delivering them to the CPU for servicing.

•

Chapter 11, “I

2C Interface,” describes the inter-IC (IIC or I2C) bus controller of the

MPC8540. This synchronous, serial, bidirectional, multi-master bus allows two-wire

connection of devices, such as microcontrollers, EEPROMs, real-time clock devices, A/D

converters and LCDs. The MPC8540 powers up in boot sequencer mode which allows the

2C controller to initialize configuration registers.

•

Chapter 12, “DUART,” describes the (dual) universal asynchronous receiver/transmitters

(UARTs) which feature a PC16552D-compatible programming model. These independent

UARTs are provided specifically to support system debugging.

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