MPC8540 datasheet(8/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

viii

Freescale Semiconductor

Contents

Paragraph

Number

Title

Page

Number

4.4.3.6

Boot Sequencer Configuration .............................................................................. 4-16

4.4.3.7

TSEC Width........................................................................................................... 4-16

4.4.3.8

TSEC1 Protocol ..................................................................................................... 4-17

4.4.3.9

TSEC2 Protocol ..................................................................................................... 4-17

4.4.3.10

RapidIO Transmit Clock Source............................................................................ 4-18

4.4.3.11

RapidIO Device ID ................................................................................................ 4-18

4.4.3.12

PCI Width Configuration....................................................................................... 4-19

4.4.3.13

PCI I/O Impedance ................................................................................................ 4-19

4.4.3.14

PCI Arbiter Configuration ..................................................................................... 4-19

4.4.3.15

PCI Debug Configuration ...................................................................................... 4-20

4.4.3.16

PCI-X Configuration ............................................................................................. 4-20

4.4.3.17

Memory Debug Configuration .............................................................................. 4-20

4.4.3.18

DDR Debug Configuration.................................................................................... 4-21

4.4.3.19

PCI/PCI-X Output Hold Configuration ................................................................. 4-21

4.4.3.20

Local Bus Output Hold Configuration .................................................................. 4-22

4.4.3.21

General-Purpose POR Configuration .................................................................... 4-23

4.4.4

Clocking..................................................................................................................... 4-23

4.4.4.1

System Clock/PCI Clock ....................................................................................... 4-23

4.4.4.2

RapidIO Clocks ..................................................................................................... 4-24

4.4.4.3

Ethernet Clocks...................................................................................................... 4-25

4.4.4.4

Real Time Clock .................................................................................................... 4-25

Part II

e500 Core Complex and L2 Cache

Chapter 5

Core Complex Overview

5.1

Overview.......................................................................................................................... 5-1

5.1.1

Upward Compatibility ................................................................................................. 5-3

5.1.2

Core Complex Summary ............................................................................................. 5-3

5.2

e500 Processor and System Version Numbers................................................................. 5-4

5.3

Features ............................................................................................................................ 5-5

5.4

Instruction Set ................................................................................................................ 5-12

5.5

Instruction Flow .............................................................................................................5-14

5.5.1

Initial Instruction Fetch.............................................................................................. 5-14

5.5.2

Branch Detection and Prediction ............................................................................... 5-14

5.5.3

e500 Execution Pipeline ............................................................................................ 5-15

5.6

Programming Model ...................................................................................................... 5-18

5.7

On-Chip Cache Implementation .................................................................................... 5-20

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