MPC8540 datasheet(13/1302 Pages) FREESCALE

13 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

xiii

Contents

Paragraph

Number

Title

Page

Number

7.10.2.1

ECC Errors............................................................................................................. 7-35

7.10.2.2

Tag Parity Errors.................................................................................................... 7-36

Part III

Memory and I/O Interfaces

Chapter 8

e500 Coherency Module

8.1

Introduction...................................................................................................................... 8-1

8.1.1

Overview...................................................................................................................... 8-1

8.1.2

Features ........................................................................................................................ 8-2

8.2

Memory Map/Register Definition ................................................................................... 8-2

8.2.1

Register Descriptions ................................................................................................... 8-3

8.2.1.1

ECM CCB Address Configuration Register (EEBACR) ........................................ 8-3

8.2.1.2

ECM CCB Port Configuration Register (EEBPCR) ............................................... 8-4

8.2.1.3

ECM Error Detect Register (EEDR) ....................................................................... 8-5

8.2.1.4

ECM Error Enable Register (EEER) ....................................................................... 8-6

8.2.1.5

ECM Error Attributes Capture Register (EEATR) .................................................. 8-7

8.2.1.6

ECM Error Address Capture Register (EEADR) .................................................... 8-8

8.3

Functional Description..................................................................................................... 8-9

8.3.1

I/O Arbiter.................................................................................................................... 8-9

8.3.2

CCB Arbiter................................................................................................................. 8-9

8.3.3

Transaction Queue ....................................................................................................... 8-9

8.3.4

Global Data Multiplexor............................................................................................ 8-10

8.3.5

CCB Interface ............................................................................................................ 8-10

8.4

Initialization/Application Information ........................................................................... 8-10

Chapter 9

DDR Memory Controller

9.1

Introduction...................................................................................................................... 9-1

9.2

Features ............................................................................................................................ 9-2

9.2.1

Modes of Operation ..................................................................................................... 9-3

9.3

External Signal Descriptions ........................................................................................... 9-3

9.3.1

Signals Overview ......................................................................................................... 9-3

9.3.2

Detailed Signal Descriptions ....................................................................................... 9-5

9.3.2.1

Memory Interface Signals........................................................................................ 9-5

9.3.2.2

Clock Interface Signals............................................................................................ 9-8

9.3.2.3

Debug Signals .......................................................................................................... 9-8

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