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ADC3561 数据表(PDF) 42 Page - Texas Instruments |
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ADC3561 数据表(HTML) 42 Page - Texas Instruments |
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42 / 85 page  8.3.4.7 Output Formatting with Decimation When using decimation, the output data is formatted as shown in Figure 8-39 (complex decimation) and Figure 8-40 (real decimation). FCLK Serial LVDS 1-Wire (16x Serialization) Serial LVDS 2-Wire (8x Serialization) DA1 DA0 DB1 DB0 Used in Single Band Serial LVDS 1/2-Wire (32x Serialization) FCLK DA0 DB0 FCLK DA0 DCLK DCLK BQ <15:0> AQ <15:0> BI <15:0> AI <15:0> BQ <15:0> AQ <15:0> BI <15:0> AI <15:0> DCLK BI D13 BI D11 BI D9 BI D7 BI D5 BI D3 BI D1 BI D12 BI D10 BI D8 BI D6 BI D4 BI D2 BI D0 BQ D13 BQ D11 BQ D9 BQ D7 BQ D5 BQ D3 BQ D12 BQ D10 BQ D8 BQ D6 BQ D4 BQ D2 BQ D1 BQ D0 AI D13 AI D11 AI D9 AI D7 AI D5 AI D3 AI D1 AI D12 AI D10 AI D8 AI D6 AI D4 AI D2 AI D0 AQ D13 AQ D11 AQ D9 AQ D7 AQ D5 AQ D3 AQ D12 AQ D10 AQ D8 AQ D6 AQ D4 AQ D2 AQ D1 AQ D0 BI D15 BI D14 AI D15 AI D14 BQ D15 BQ D14 AQ D15 AQ D14 Used in Single Band Only used for Dual Band Only used for Dual Band Only used for Dual Band Figure 8-39. Output Data Format in Complex Decimation Table 8-4 illustrates the output interface data rate along with the corresponding DCLK/DCLKIN and FCLK frequencies based on output resolution (R), number of SLVDS lanes (L) and complex decimation setting (N). Furthermore the table shows an actual lane rate example for the 2-, 1- and 1/2-wire interface, 16-bit output resolution and complex decimation by 4. Table 8-4. Serial LVDS Lane Rate Examples with Complex Decimation and 16-bit Output Resolution DECIMATION SETTING ADC SAMPLING RATE OUTPUT RESOLUTION # of WIRES FCLK DCLKIN, DCLK DA/B0,1 N FS R L FS / N [DA/B0,1] / 2 FS x 2 x R / L / N 4 65 MSPS 16 2 16.25 MHz 130 MHz 260 MHz 1 260 MHz 520 MHz 62.5 MSPS 1/2 15.625 MHz 500 MHz 1000 MHz ADC3561, ADC3562, ADC3563 SBAS990B – FEBRUARY 2021 – REVISED OCTOBER 2022 www.ti.com 42 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADC3561 ADC3562 ADC3563 |
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