ADC3561 datasheet(13/85 Pages) TI

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6.8 Timing Requirements (continued)

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to

TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, external 1.6 V reference, and

–1-dBFS differential input, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

tCD

DCLK rising edge to output data delay,

2-wire SLVDS

Fout = 10 MSPS, DA/B0,1 = 80 MBPS

0.0

0.1

Fout = 25 MSPS, DA/B0,1 = 200 MBPS

0.0

0.1

Fout = 65 MSPS, DA/B0,1 = 520 MBPS

0.0

0.1

DCLK rising edge to output data delay,

1-wire SLVDS

Fout = 10 MSPS, DA/B0 = 160 MBPS

0.0

0.1

Fout = 25 MSPS, DA/B0 = 400 MBPS

0.0

0.1

Fout = 62.5 MSPS, DA/B0= 1000 MBPS

-0.6

0.1

DCLK rising edge to output data delay,

1/2-wire SLVDS

Fout = 5 MSPS, DA0 = 160 MBPS

0.0

0.1

Fout = 10 MSPS, DA0 = 320 MBPS

0.0

0.1

Fout = 25 MSPS, DA0 = 800 MBPS

0.0

0.1

tDV

Data valid, 2-wire SLVDS

Fout = 10 MSPS, DA/B0,1 = 80 MBPS

11.9

12.1

Fout = 25 MSPS, DA/B0,1 = 200 MBPS

4.5

4.6

Fout = 65 MSPS, DA/B0,1 = 520 MBPS

1.4

1.5

Data valid, 1-wire SLVDS

Fout = 10 MSPS, DA/B0 = 160 MBPS

5.7

5.8

Fout = 25 MSPS, DA/B0 = 400 MBPS

2.0

2.1

Fout = 62.5 MSPS, DA/B0= 1000 MBPS

0.5

0.6

Data valid, 1/2-wire SLVDS

Fout = 5 MSPS, DA0 = 160 MBPS

5.7

5.8

Fout = 10 MSPS, DA0 = 320 MBPS

2.7

2.8

Fout = 25 MSPS, DA0 = 800 MBPS

0.8

0.9

SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input

fCLK(SCLK) Serial clock frequency

MHz

tSU(SEN)

SEN to rising edge of SCLK

tH(SEN)

SEN from rising edge of SCLK

tSU(SDIO)

SDIO to rising edge of SCLK

tH(SDIO)

SDIO from rising edge of SCLK

SERIAL PROGRAMMING INTERFACE (SDIO) - Output

t(OZD)

SDIO tri-state to driven

3.9

10.8

t(ODZ)

SDIO data to tri-state

3.4

t(OD)

SDIO valid from falling edge of SCLK

3.9

10.8

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ADC3561, ADC3562, ADC3563

SBAS990B – FEBRUARY 2021 – REVISED OCTOBER 2022

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