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ADC3561 数据表(PDF) 12 Page - Texas Instruments |
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ADC3561 数据表(HTML) 12 Page - Texas Instruments |
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12 / 85 page  6.8 Timing Requirements Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, external 1.6 V reference, and –1-dBFS differential input, unless otherwise noted PARAMETER TEST CONDITIONS MIN NOM MAX UNIT ADC Timing Specifications tAD Aperture Delay 0.85 ns tA Aperture Jitter square wave clock with fast edges 180 fs tJ Jitter on DCLKIN ± 50 ps tACQ Signal acquisition period, referenced to sampling clock falling edge FS = 65 Msps -TS/4 Sampling Clock Period FS = 25 Msps -TS/2 FS = 10 Msps -TS/2 tCONV Signal conversion period, referenced to sampling clock falling edge FS = 65 Msps +TS × 5/8 Sampling Clock Period FS = 25 Msps +TS × 3/8 FS = 10 Msps +TS × 1/5 Wake up time Time to valid data after coming out of power down. Internal reference. Bandgap reference enabled, single ended clock 17.6 us Bandgap reference enabled, differential clock 12.9 Bandgap reference disabled, single ended clock 2.2 ms Bandgap reference disabled, differential clock 2.2 Time to valid data after coming out of power down. External 1.6V reference. Bandgap reference enabled, single ended clock 15.9 us Bandgap reference enabled, differential clock 12.9 Bandgap reference disabled, single ended clock 1.7 ms Bandgap reference disabled, differential clock 1.7 tS,SYNC Setup time for SYNC input signal Referenced to sampling clock rising edge 500 ps tH,SYNC Hold time for SYNC input signal 600 ADC Latency Signal input to data output 2-wire SLVDS 2 Clock cycles 1-wire SLVDS 1 1/2-wire SLVDS 1 Add. Latency Real decimation by 2 21 Output clock cycles Complex decimation by 2 22 Real or complex decimation by 4, 8, 16, 32 23 Interface Timing: Serial LVDS Interface tPD Propagation delay: sampling clock falling edge to DCLK rising edge Delay between sampling clock falling edge to DCLKIN falling edge < 2.5ns. TDCLK = DCLK period tCDCLK = Sampling clock falling edge to DCLKIN falling edge 2 + TDCLK + tCDCLK 3 + TDCLK + tCDCLK 4 + TDCLK + tCDCLK ns Delay between sampling clock falling edge to DCLKIN falling edge >= 2.5ns. TDCLK = DCLK period tCDCLK = Sampling clock falling edge to DCLKIN falling edge 2 + tCDCLK 3 + tCDCLK 4 + tCDCLK ADC3561, ADC3562, ADC3563 SBAS990B – FEBRUARY 2021 – REVISED OCTOBER 2022 www.ti.com 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADC3561 ADC3562 ADC3563 |
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