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ADC3561 数据表(PDF) 62 Page - Texas Instruments

部件名 ADC3561
功能描述  ADC356x 16-Bit, 0.5-MSPS to 65-MSPS, Low-Noise, Low Power ADC
PDF  85 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

ADC3561 数据表(HTML) 62 Page - Texas Instruments

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Figure 8-66. Register 0x1E
7
6
5
4
3
2
1
0
0
0
0
0
LVDS DATA DEL
LVDS DCLK DEL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-28. Register 0x1E Field Descriptions
Bit
Field
Type
Reset
Description
7-4
0
R/W
0
Must write 0
3-2
LVDS DATA DEL
R/W
00
These bits adjust the output timing of the SLVDS output data.
00: no delay
01: Data advanced by 50 ps
10: Data delayed by 50 ps
11: Data delayed by 100 ps
1-0
LVDS DCLK DEL
R/W
00
These bits adjust the output timing of the SLVDS DCLK output.
00: no delay
01: DCLK advanced by 50 ps
10: DCLK delayed by 50 ps
11: DCLK delayed by 100 ps
Figure 8-67. Register 0x20/21/22
7
6
5
4
3
2
1
0
FCLK PAT [7:0]
FCLK PAT [15:8]
0
SCR EN
0
0
FCLK PAT [19:16]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-29. Register 0x20/21/22 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
FCLK PAT [19:0]
R/W
0xFFC00
These bits can adjust the duty cycle of the FCLK. In decimation
bypass mode the FCLK pattern gets adjusted automatically for
the different output resolutions. Table 8-30 shows the proper
FCLK pattern values for 1-wire and 1/2-wire in real/complex
decimation.
6
SCR EN
R/W
0
This bit enables the output data scrambler. Digital bypass (0x24,
D2) needs to be set as well.
0: Output scrambling disabled
1: Output scrambling enabled
Table 8-30. FCLK Pattern for different resolution based on interface
DECIMATION
OUTPUT RESOLUTION
2-WIRE
1-WIRE
1/2-WIRE
REAL DECIMATION
14-bit
Use Default
0xFE000
Use Default
16-bit
0xFF000
18-bit
0xFF800
20-bit
0xFFC00
COMPLEX
DECIMATION
14-bit
0xFFFFF
0xFFFFF
16-bit
18-bit
20-bit
ADC3561, ADC3562, ADC3563
SBAS990B – FEBRUARY 2021 – REVISED OCTOBER 2022
www.ti.com
62
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: ADC3561 ADC3562 ADC3563



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