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P89LPC952FBD 数据表(PDF) 39 Page - NXP Semiconductors |
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P89LPC952FBD 数据表(HTML) 39 Page - NXP Semiconductors |
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39 / 66 page ![]() 9397 750 14716 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 01— 16 September 2005 39 of 66 Philips Semiconductors P89LPC952 8-bit microcontroller with 10-bit ADC 7.22.1 Internal reference voltage An internal reference voltage generator may supply a default reference when a single comparator input pin is used. The value of the internal reference voltage, referred to as Vref(bg), is 1.23 V ± 10 %. 7.22.2 Comparator interrupt Each comparator has an interrupt flag contained in its configuration register. This flag is set whenever the comparator output changes state. The flag may be polled by software or may be used to generate an interrupt. The two comparators use one common interrupt vector. If both comparators enable interrupts, after entering the interrupt service routine, the user needs to read the flags to determine which comparator caused the interrupt. 7.22.3 Comparators and power reduction modes Either or both comparators may remain enabled when Power-down or Idle mode is activated, but both comparators are disabled automatically in Total Power-down mode. If a comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake-up the processor. If the comparator output to a pin is enabled, the pin should be configured in the push-pull mode in order to obtain fast switching times while in Power-down mode. The reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place. Comparators consume power in Power-down and Idle modes, as well as in the normal operating mode. This fact should be taken into account when system power consumption is an issue. To minimize power consumption, the user can disable the comparators via PCONA.5, or put the device in Total Power-down mode. Fig 14. Comparator input and output connections comparator 1 CP1 CN1 (P0.4) CIN1A (P0.3) CIN1B (P0.5) CMPREF Vref(bg) OE1 change detect CO1 CMF1 interrupt 002aaa904 CMP1 (P0.6) EC change detect CMF2 comparator 2 OE2 CO2 CMP2 (P0.0) CP2 CN2 (P0.2) CIN2A (P0.1) CIN2B |
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