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P89LPC952FBD 数据表(PDF) 41 Page - NXP Semiconductors |
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P89LPC952FBD 数据表(HTML) 41 Page - NXP Semiconductors |
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41 / 66 page ![]() 9397 750 14716 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 01— 16 September 2005 41 of 66 Philips Semiconductors P89LPC952 8-bit microcontroller with 10-bit ADC 7.25 Additional features 7.25.1 Software reset The SRST bit in AUXR1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. Care should be taken when writing to AUXR1 to avoid accidental software resets. 7.25.2 Dual data pointers The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address used with certain instructions. The DPS bit in the AUXR1 register selects one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register, without the possibility of inadvertently altering other bits in the register. 7.26 Flash program memory 7.26.1 General description The P89LPC952 flash memory provides in-circuit electrical erasure and programming. The flash can be erased, read, and written as bytes. The Sector and Page Erase functions can erase any flash sector (1 kB) or page (64 bytes). The Chip Erase operation will erase the entire program memory. ICP using standard commercial programmers is available. In addition, IAP and byte-erase allows code memory to be used for non-volatile data storage. On-chip erase and write timing generation contribute to a user-friendly programming interface. The P89LPC952 flash reliably stores memory contents even after 100,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. The P89LPC952 uses VDD as the supply voltage to perform the Program/Erase algorithms. (1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed sequence. Fig 15. Watchdog timer in Watchdog mode (WDTE = 1) PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK WDCON (A7H) SHADOW REGISTER PRESCALER 002aaa905 8-BIT DOWN COUNTER WDL (C1H) watchdog oscillator PCLK ÷32 MOV WFEED1, #0A5H MOV WFEED2, #05AH reset(1) |
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