 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
P89LPC952FBD 数据表(PDF) 53 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
P89LPC952FBD 数据表(HTML) 53 Page - NXP Semiconductors |
|
|
53 / 66 page  9397 750 14716 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 01— 16 September 2005 53 of 66 Philips Semiconductors P89LPC952 8-bit microcontroller with 10-bit ADC Table 12: Dynamic characteristics (18 MHz) VDD = 3.0 V to 3.6 V unless otherwise specified. Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified. [1] [2] Symbol Parameter Conditions Variable clock fosc =18MHz Unit Min Max Min Max fosc(RC) internal RC oscillator frequency nominal f = 7.3728 MHz trimmed to ± 1 % at Tamb =25 °C; clock doubler option = OFF (default) 7.189 7.557 7.189 7.557 MHz nominal f = 14.7456 MHz; clock doubler option = ON 14.378 15.114 14.378 15.114 MHz fosc(WD) internal watchdog oscillator frequency 320 520 320 520 kHz fosc oscillator frequency 0 18 - - MHz Tcy(CLK) clock cycle time see Figure 18 55 - - - ns fCLKLP active frequency on pin CLKLP 0 8 - - MHz Glitch filter tgr glitch rejection time P1.5/RST pin - 50 - 50 ns any pin except P1.5/RST - 15 - 15 ns tsa signal acceptance time P1.5/RST pin 125 - 125 - ns any pin except P1.5/RST 50 - 50 - ns External clock tCHCX clock HIGH time see Figure 18 22 Tcy(CLK) − tCLCX 22 - ns tCLCX clock LOW time see Figure 18 22 Tcy(CLK) − tCHCX 22 - ns tCLCH clock rise time see Figure 18 -5 - 5 ns tCHCL clock fall time see Figure 18 -5 - 5 ns Shift register (UART mode 0) TXLXL serial port clock cycle time see Figure 17 16Tcy(CLK) - 888 - ns tQVXH output data set-up to clock rising edge time see Figure 17 13Tcy(CLK) - 722 - ns tXHQX output data hold after clock rising edge time see Figure 17 -Tcy(CLK) + 20 - 75 ns tXHDX input data hold after clock rising edge time see Figure 17 -0 - 0 ns tXHDV input data valid to clock rising edge time see Figure 17 150 - 150 - ns SPI interface fSPI SPI operating frequency slave 0 CCLK ⁄ 6 0 3.0 MHz master - CCLK ⁄ 4 - 4.5 MHz TSPICYC SPI cycle time see Figure 19, 20, 21, 22 slave 6 ⁄ CCLK - 333 - ns master 4 ⁄ CCLK - 222 - ns |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
