SST26VF032BEUI datasheet(28/76 Pages) MICROCHIP

28 / 76 page

SST26VF032BEUI

DS20006152A-page 28

 2019 Microchip Technology Inc.

5.21

SPI Quad Page-Program

The SPI Quad Page-Program instruction programs up

to 256 Bytes of data in the memory. The data for the

selected page address must be in the erased state

(FFH) before initiating the SPI Quad Page-Program

operation. A SPI Quad Page-Program applied to a pro-

tected

memory

area

will

ignored.

SST26VF032BEUI requires the ICO bit in the configu-

ration register to be set to ‘1’ prior to executing the com-

mand. Prior to the program operation, execute the

WREN instruction.

To execute a SPI Quad Page-Program operation, the

host drives CE# low then sends the SPI Quad Page-

Program command cycle (32H), three address cycles

followed by the data to be programmed, then drives

CE# high. The programmed data must be between 1 to

256 Bytes and in whole Byte increments. The com-

mand cycle is eight clocks long, the address and data

cycles are each two clocks long, most significant bit

first. Poll the BUSY bit in the Status register, or wait TPP,

for the completion of the internal, self-timed, Write

operation.See Figure 5-27.

When executing SPI Quad Page-Program, the memory

range for the SST26VF032BEUI is divided into 256

Byte page boundaries. The device handles shifting of

more than 256 Bytes of data by maintaining the last 256

Bytes of data as the correct data to be programmed. If

the target address for the SPI Quad Page-Program

instruction is not the beginning of the page boundary

(A[7:0] are not all zero), and the of bytes of data input

exceeds or overlaps the end of the address of the page

boundary, the excess data inputs wrap around and will

be programmed at the start of that target page.

FIGURE 5-27:

SPI QUAD PAGE-PROGRAM SEQUENCE

5.22

Write-Suspend and Write-Resume

Write-Suspend allows the interruption of Sector-Erase,

Block-Erase, SPI Quad Page-Program, or Page-Pro-

gram operations in order to erase, program, or read

data in another portion of memory. The original opera-

tion can be continued with the Write-Resume com-

mand. This operation is supported in both SQI and SPI

protocols.

Only one write operation can be suspended at a time;

if an operation is already suspended, the device will

ignore the Write-Suspend command. Write-Suspend

during Chip-Erase is ignored; Chip-Erase is not a valid

command while a write is suspended. The Write-

Resume command is ignored until any write operation

(Program or Erase) initiated during the Write-Suspend

is complete. The device requires a minimum of 500 µs

between each Write-Suspend command.

5.23

Write-Suspend During Sector-

Erase or Block-Erase

Issuing a Write-Suspend instruction during Sector-

Erase or Block-Erase allows the host to program or

read any sector that was not being erased. The device

will ignore any programming commands pointing to the

suspended sector(s). Any attempt to read from the sus-

pended sector(s) will output unknown data because the

Sector- or Block-Erase will be incomplete.

To execute a Write-Suspend operation, the host drives

CE# low, sends the Write Suspend command cycle

(B0H), then drives CE# high. The Status register indi-

cates that the erase has been suspended by changing

the WSE bit from ‘0’ to ‘1,’ but the device will not accept

another command until it is ready. To determine when

the device will accept a new command, poll the BUSY

bit in the Status register or wait TWS.

A20A16A12 A8 A4 A0 b4 b0

CE#

SIO0

SCK

012345678

16 17

MODE 3

MODE 0

91011

32H

20005218 F61.0

SIO1

SIO2

SIO3

Address

Data

Byte 1

13 14

A21 A17A13 A9 A5 A1 b5 b1 b5 b1

b5 b1

A22 A18A14A10 A6 A2 b6 b2 b6 b2

b6 b2

A23 A19 A15 A11 A7 A3 b7 b3 b7 b3

b7 b3

Data

Byte 0

Data

Byte

255

MSN LSN

b4 b0

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