SST26VF032BEUI datasheet(6/76 Pages) MICROCHIP

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SST26VF032BEUI

DS20006152A-page 6

 2019 Microchip Technology Inc.

4.0

DEVICE OPERATION

SST26VF032BEUI supports both Serial Peripheral

Interface (SPI) bus protocol and a 4-bit multiplexed SQI

bus protocol. To provide backward compatibility to tra-

ditional SPI Serial Flash devices, the device’s initial

state after a power-on reset is SPI mode which sup-

ports multi-I/O (x1/x2/x4) Read/Write commands. A

command instruction configures the device to SQI

mode. The dataflow in the SQI mode is similar to the

SPI mode, except it uses four multiplexed I/O signals

for command, address, and data sequence.

SQI Flash Memory supports both Mode 0 (0,0) and

Mode 3 (1,1) bus operations. The difference between

the two modes is the state of the SCK signal when the

bus master is in stand-by mode and no data is being

transferred. The SCK signal is low for Mode 0 and SCK

signal is high for Mode 3. For both modes, the Serial

Data I/O (SIO[3:0]) is sampled at the rising edge of the

SCK clock signal for input, and driven after the falling

edge of the SCK clock signal for output. The traditional

SPI protocol uses separate input (SI) and output (SO)

data signals as shown in Figure 4-1. The SQI protocol

uses four multiplexed signals, SIO[3:0], for both data in

and data out, as shown in Figure 4-2. This means the

SQI protocol quadruples the traditional bus transfer

speed at the same clock frequency, without the need

for more pins on the package.

The SST26VF032BEUI is pre-programmed with a

globally unique EUI-48 and EUI-64 identifiers. The

addresses are located in the Serial Flash Discoverable

Parameters (SFDP) table and accessible via the SFDP

read instruction. Refer to See “Pre-Programmed EUI-

48 and EUI-64 Address” on page 72 for address loca-

tions and description.

FIGURE 4-1:

SPI PROTOCOL (TRADITIONAL 25 SERIES SPI DEVICE)

FIGURE 4-2:

SQI SERIAL QUAD I/O PROTOCOL

4.1

Device Protection

SST26VF032BEUI offer a flexible memory protection

scheme that allows the protection state of each individ-

ual block to be controlled separately. In addition, the

Write-Protection Lock-Down register prevents any

change of the lock status during device operation. To

avoid inadvertent writes during power-up, the device is

write-protected by default after a power-on reset cycle.

A Global Block-Protection Unlock command offers a

single command cycle that unlocks the entire memory

array for faster manufacturing throughput.

For extra protection, there is an additional non-volatile

Protection register bits for each individual block. Each

of the corresponding lock-down bits are one time pro-

grammable (OTP)—once written, they cannot be

erased. Data that had been previously programmed

into these blocks cannot be altered by programming or

erase and is not reversible

4.1.1

INDIVIDUAL BLOCK PROTECTION

SST26VF032BEUI have a Block-Protection register

which provides a software mechanism to write-lock the

individual memory blocks and write-lock, and/or read-

lock, the individual parameter blocks. The Block-Pro-

tection register is 80 bits wide: two bits each for the

eight 8 KByte parameter blocks (write-lock and read-

lock), and one bit each for the remaining 32 KByte and

64 KByte overlay blocks (write-lock). See Table 5-6 for

address range protected per register bit.

Each bit in the Block-Protection register (BPR) can be

written to a ‘1’ (protected) or ‘0’ (unprotected). For the

parameter blocks, the most significant bit is for read-

20005218 F03.0

MODE 3

SCK

CE#

MODE 3

DON'T CARE

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MODE 0

HIGH IMPEDANCE

MSB

20005218 F04.0

MODE 3

CLK

SIO(3:0)

CE#

MODE 3

MODE 0

MSB

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