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SST26VF032BEUI 数据表(PDF) 56 Page - Microchip Technology

部件名 SST26VF032BEUI
功能描述  32 Mbit Serial Quad I/O (SQI) Flash Memory with EUI-48™ and EUI-64™ Identifier
PDF  76 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

SST26VF032BEUI 数据表(HTML) 56 Page - Microchip Technology

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SST26VF032BEUI
DS20006152A-page 56
 2019 Microchip Technology Inc.
3AH
A20:A16
08H
(1-1-4) Fast Read Number of Wait states (dummy clocks) needed
before valid output
01000b: 8 dummy bits are needed with a single input opcode & address
and quad output data Fast Read Instruction
A23:A21
(1-1-4) Fast Read Number of Mode Bits
000b: No mode bits are needed with a single input opcode & address and
quad output data Fast Read Instruction
3BH
A31:A24
6BH
(1-1-4) Fast Read Opcode
Opcode for single input opcode & address and quad output data Fast
Read.
JEDEC Flash Parameter Table: 4th DWORD
3CH
A4:A0
08H
(1-1-2) Fast Read Number of Wait states (dummy clocks) needed
before valid output
01000b: 8 dummy clocks are needed with a single input opcode, address
and dual output data fast read instruction.
A7:A5
(1-1-2) Fast Read Number of Mode Bits
000b: No mode bits are needed with a single input opcode & address and
quad output data Fast Read Instruction
3DH
A15:A8
3BH
(1-1-2) Fast Read Opcode
Opcode for single input opcode& address and dual output data Fast Read.
3EH
A20:A16
80H
(1-2-2) Fast Read Number of Wait states (dummy clocks) needed
before valid output
00010b: 0 clocks of dummy cycle.
A23:A21
(1-2-2) Fast Read Number of Mode Bits (in clocks)
010b: 4 clocks of mode bits are needed
3FH
A31:A24
BBH
(1-2-2) Fast Read Opcode
Opcode for single input opcode, dual input address, and dual output data
Fast Read.
JEDEC Flash Parameter Table: 5th DWORD
40H
A0
FEH
Supports (2-2-2) Fast Read
Device supports dual input opcode& address and dual output data Fast
Read.
0:
(2-2-2) Fast Read NOT supported.
1:
(2-2-2) Fast Read supported.
A3:A1
Reserved. Bits default to all 1’s.
A4
Supports (4-4-4) Fast Read
Device supports Quad input opcode & address and quad output data
Fast Read.
0:
(4-4-4) Fast Read NOT supported.
1:
(4-4-4) Fast Read supported.
A7:A5
Reserved. Bits default to all 1’s.
41H
A15:A8
FFH
Reserved. Bits default to all 1’s.
42H
A23:A16
FFH
Reserved. Bits default to all 1’s.
43H
A31:A24
FFH
Reserved. Bits default to all 1’s.
TABLE 11-1:
SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (4 OF 16)
Address
Bit Address
Data
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