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TDA4VL...ALZQ1 数据表(PDF) 32 Page - Texas Instruments

部件名 TDA4VL...ALZQ1
功能描述  TDA4VE TDA4AL TDA4VL Jacinto™ Processors, Silicon Revision 1.0
PDF  251 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TDA4VL...ALZQ1 数据表(HTML) 32 Page - Texas Instruments

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Table 6-2. Pin Attributes (ALZ Package) (continued)
Ball
Num [1]
Ball
Name [2]
PADCFG Register [13]
PADCFG Address [14]
Signal
Name [3]
Mux
Mode [4]
Signal
Type [5]
I/O
Voltage [6]
Ball State
DURING
Reset
(RX/TX/PULL) [7]
Ball State
AFTER
Reset
(RX/TX/PULL) [8]
Mux
Mode
AFTER
Reset [9]
Power [10]
Voltage
Buffer
Type [11]
IO
RET [12]
T25
MCASP0_AXR7
PADCFG:
PADCONFIG_35
0x4301C08C
MCAN5_TX
0
O
1.8 V/3.3 V
Off / Off / Off
Off / Off / Off
7
VDDSHV2
LVCMOS
Yes
MCASP0_AXR7
1
IO
MCASP4_ACLKR
3
IO
GPMC0_A0
5
OZ
RGMII1_TD0
6
O
GPIO0_35
7
IO
GPMC0_A14
8
OZ
EHRPWM3_A
9
IO
UART4_RXD
11
I
GPMC0_CSn2
12
O
USB0_DRVVBUS
14
O
W24
MCASP0_AXR8
PADCFG:
PADCONFIG_36
0x4301C090
MCAN5_RX
0
I
1.8 V/3.3 V
Off / Off / Off
Off / Off / Off
7
VDDSHV2
LVCMOS
Yes
MCASP0_AXR8
1
IO
MCASP4_AFSR
3
IO
GPMC0_A1
5
OZ
RGMII1_TD1
6
O
GPIO0_36
7
IO
RMII1_RXD0
8
I
EHRPWM_TZn_IN3
9
I
UART4_TXD
11
O
AA25
MCASP0_AXR9
PADCFG:
PADCONFIG_37
0x4301C094
MCAN6_TX
0
O
1.8 V/3.3 V
Off / Off / Off
Off / Off / Off
7
VDDSHV2
LVCMOS
Yes
MCASP0_AXR9
1
IO
MCASP4_AXR4
2
IO
GPMC0_A2
5
OZ
RGMII1_TD2
6
O
GPIO0_37
7
IO
RMII1_RXD1
8
I
EHRPWM3_SYNCO
9
O
UART4_CTSn
11
I
V25
MCASP0_AXR10
PADCFG:
PADCONFIG_38
0x4301C098
MCAN6_RX
0
I
1.8 V/3.3 V
Off / Off / Off
Off / Off / Off
7
VDDSHV2
LVCMOS
Yes
MCASP0_AXR10
1
IO
GPMC0_A3
5
OZ
RGMII1_TD3
6
O
GPIO0_38
7
IO
RMII1_CRS_DV
8
I
EHRPWM3_SYNCI
9
I
UART4_RTSn
11
O
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1
SPRSP62 – DECEMBER 2022
www.ti.com
32
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Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1



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