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TDA4VL...ALZQ1 数据表(PDF) 91 Page - Texas Instruments |
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TDA4VL...ALZQ1 数据表(HTML) 91 Page - Texas Instruments |
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91 / 251 page  Table 6-109. Sysboot Signal Descriptions (continued) SIGNAL NAME PIN TYPE DESCRIPTION ALZ PIN MCU_BOOTMODE05 I MCU Bootmode Pin 5 C28 MCU_BOOTMODE06 I MCU Bootmode Pin 6 B24 MCU_BOOTMODE07 I MCU Bootmode Pin 7 D25 MCU_BOOTMODE08 I MCU Bootmode Pin 8 C25 MCU_BOOTMODE09 I MCU Bootmode Pin 9 C24 6.3.30.2 Clock Table 6-110. Clock0 Signal Descriptions SIGNAL NAME PIN TYPE DESCRIPTION ALZ PIN WKUP_LF_CLKIN I Low Frequency (32.768 KHz) Oscillator Input J27 WKUP_OSC0_XI I High Frequency Oscillator Input H28 WKUP_OSC0_XO O High Frequency Oscillator Output J28 Table 6-111. Clock1 Signal Descriptions SIGNAL NAME PIN TYPE DESCRIPTION ALZ PIN OSC1_XI I High Frequency Oscillator Input M28 OSC1_XO O High Frequency Oscillator Output L28 6.3.30.3 System Table 6-112. MCU System Signal Descriptions SIGNAL NAME PIN TYPE DESCRIPTION ALZ PIN MCU_CLKOUT0 OZ Reference clock output for Ethernet PHYs (50MHz or 25MHz) F25 MCU_EXT_REFCLK0 I External system clock input F27, K26 MCU_OBSCLK0 O Observation clock output for test and debug purposes only C26, F25 MCU_PORz I MCU Domain Cold Reset G23 MCU_RESETSTATz O MCU Domain Warm Reset status output A23 MCU_RESETz I MCU Domain Warm Reset A26 MCU_SAFETY_ERRORn IO Error signal output from MCU Domain ESM J23 MCU_SYSCLKOUT0 O MCU Domain system clock output for test and debug purposes only F27 Table 6-113. System Signal Descriptions SIGNAL NAME PIN TYPE DESCRIPTION ALZ PIN AUDIO_EXT_REFCLK0 IO External clock routed to ATL or McASP as one of the selectable input clock sources, or as a output clock output for ATL or McASP AD24 AUDIO_EXT_REFCLK1 IO External clock routed to ATL or McASP as one of the selectable input clock sources, or as a output clock output for ATL or McASP Y25 EXTINTn I External Interrupt AG24 EXT_REFCLK1 I External clock input to Main Domain, routed to Timer clock muxes as one of the selectable input clock sources for Timer/WDT modules, or as reference clock to MAIN_PLL2 (PER1 PLL) AD28 GPMC0_FCLK_MUX O GPMC functional clock output selected through a mux logic AD27 www.ti.com TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1 SPRSP62 – DECEMBER 2022 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 91 Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1 |
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