TDA4VL...ALZQ1 datasheet(1/251 Pages) TI

部件名	TDA4VL...ALZQ1

功能描述	TDA4VE TDA4AL TDA4VL Jacinto™ Processors, Silicon Revision 1.0

PDF	251 Pages

Scroll/Zoom	100%

制造商	TI [Texas Instruments]

网页	http://www.ti.com

标志

1 / 251 page

TDA4VE TDA4AL TDA4VL Jacinto™ Processors, Silicon Revision 1.0

1 Features

Processor cores:

• Two C7x floating point, vector DSP, up to 1.0 GHz,

160 GFLOPS, 512 GOPS

• Deep-learning matrix multiply accelerator (MMA),

up to 8 TOPS (8b) at 1.0 GHz

• Vision Processing Accelerators (VPAC) with Image

Signal Processor (ISP) and multiple vision assist

accelerators

• Depth and Motion Processing Accelerators

(DMPAC)

• Dual 64-bit Arm® Cortex®-A72 microprocessor

subsystem at up to 2 GHz

– 1MB shared L2 cache per dual-core Cortex®-

A72 cluster

– 32KB L1 DCache and 48KB L1 ICache per

Cortex®-A72 core

• Up to Six Arm® Cortex®-R5F MCUs at up to 1.0

GHz

– 16K I-Cache, 16K D-Cache, 64K L2 TCM

– Two Arm® Cortex®-R5F MCUs in isolated MCU

subsystem

– Four (TDA4VE) or Two (TDA4AL/TDA4VL)

Arm® Cortex®-R5F MCUs in general compute

partition

• GPU IMG BXS-64-4, 256kB Cache, up to 800

MHz, 50 GFLOPS, 4 GTexels/s (TDA4VE and

TDA4VL)

• Custom-designed interconnect fabric supporting

near max processing entitlement

Memory subsystem:

• Up to 4MB of on-chip L3 RAM with ECC and

coherency

– ECC error protection

– Shared coherent cache

– Supports internal DMA engine

• Up to Two External Memory Interface (EMIF)

modules with ECC

– Supports LPDDR4 memory types

– Supports speeds up to 4266 MT/s

– Two (TDA4VE) or One (TDA4AL/TDA4VL) 32-

bit data bus with inline ECC up to 17 GB/s per

EMIF

• General-Purpose Memory Controller (GPMC)

• One (TDA4AL/TDA4VL) or Two (TDA4VE) 512KB

on-chip SRAM in MAIN domain, protected by ECC

Functional Safety:

• Functional Safety-Compliant targeted (on select

part numbers)

• Developed for functional safety applications

• Documentation available to aid ISO 26262

functional safety system design up to ASIL-D/SIL-3

targeted

• Systematic capability up to ASIL-D/SIL-3 targeted

• Hardware integrity up to ASIL-D/SIL-3 targeted for

MCU Domain

• Hardware integrity up to ASIL-B/SIL-2 targeted for

Main Domain

• Hardware integrity up to ASIL-D/SIL-3 targeted

for Extended MCU (EMCU) portion of the Main

Domain

• Safety-related certification

– ISO 26262 planned

Device security (on select part numbers):

• Secure boot with secure runtime support

• Customer programmable root key, up to RSA-4K

or ECC-512

• Embedded hardware security module

• Crypto hardware accelerators – PKA with ECC,

AES, SHA, RNG, DES and 3DES

High speed serial interfaces:

• One PCI-Express® (PCIe) Gen3 controllers

– Up to four lanes per controller

– Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3

(8.0GT/s) operation with auto-negotiation

• One USB 3.0 dual-role device (DRD) subsystem

– Enhanced SuperSpeed Gen1 Port

– Supports Type-C switching

– Independently configurable as USB host, USB

peripheral, or USB DRD

• Two CSI2.0 4L RX plus Two CSI2.04L TX

Automotive interfaces:

• Twenty Modular Controller Area Network (MCAN)

modules with full CAN-FD support

Display subsystem:

• One (TDA4AL/TDA4VL) or Two (TDA4VE) DSI 4L

TX (up to 2.5K)

• One eDP 4L (TDA4VE/TDA4VL)

• One DPI

Audio interfaces:

• Five Multichannel Audio Serial Port (MCASP)

modules

TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1

SPRSP62 – DECEMBER 2022

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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