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TDA4VL...ALZQ1 数据表(PDF) 4 Page - Texas Instruments |
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TDA4VL...ALZQ1 数据表(HTML) 4 Page - Texas Instruments |
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4 / 251 page  3.1 Functional Block Diagram Figure 3-1 is functional block diagram for the device. MCU_FSS NAVSS MSMC 1× A72SS 2MB L2 2× Arm Cortex-A72 DebugSS PLLs 20 TIMER × CTRL_MMR 10 WWDT × RINGACC Proxy Spinlock PSI-L 2 TIMER_MGR × DDRSS 2× 32b + in-line ECC + MFLAG MCRC UDMA-P CPTS 3 INTA × 2 MCU_ADC × (1 2b/4MSPS) 8ch/ 2 MCU_MCAN × 3 MCU_MCSPI × 1× MCU_UART 2 MCU_I2C × MCU Internal Diagnostics 3x MCU_DCC R5FSS R5F R5F I-cache 32KB TCM 64KB D-cache 32KB I-cache 32KB TCM 64KB D-cache 32KB WKUP_SMS ROM 160K M4F WKUP_PLLCTRL WKUP_PSC 2× WKUP_GPIO 1× WKUP_UART 1× WKUP_I2C WKUP/MCU Domain WKUP_CTRL_MMR 1× WKUP_ESM 1× MCU_CPSW PSI-L UDMA-P Proxy MCRC To NAVSS To MCU NAVSS MCU_PDMA INTA MAIN Domain 1 × MCU_ESM MCU NAVSS WKUP_VTM 2 Mailbox × Local Interconnect RINGACC INTA INTR Channelized FW Channelized FW AES SECMGR Interconnect intro-001 2 PVU × VIRTSS To CPSW 10× DCC ESM 2 OSPI × 2 x 512 KB SRAM 1024KB L3 RAM 10 MCU_TIMER × 3 MCU_PLL × 2 MCU_WWDT × MCU_CTRL_MMR 512B t Scra chpad RAM 2× R5FSS 1 HPB × 2 Arm × Cortex-R5F TCM 64KB 1 SERDES (4L) × 1 ATL × 2 DPHY_TX × MUX DPHY_RX 1× DRU WKUP_SA2SS MCU_SA2_UL AES3DES DBG PKA SHA WKUP_DMSS_HSM SecProxy/RA PKTDMA PSI-L + CMMU Compression 4MB SRAM with ECC 1× C71SS 512KB L2 1× C71x DSP+MMA 1 MCU_I3C × H.264/H.265 MSMC 1× C71SS 512KB L2 1× C71x DSP GPU BSX-64-4 Encode/Decode MUX A. A solid black box indicates the IP is part of the Extended MCU (eMCU). B. A dashed black box indicates that some instances of the IP are present in the eMCU and some instances are present in the non-eMCU portion of the Main Domain. Figure 3-1. Functional Block Diagram TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1 SPRSP62 – DECEMBER 2022 www.ti.com 4 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1 |
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