TDA4VL...ALZQ1 datasheet(120/251 Pages) TI

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VDDA_1P8_<phy> are 1.8-V analog domains supporting multiple serial PHY interfaces. A low noise, analog supply is recommended

to provide best signal integrity, interface performance and spec compliance. If any of these interfaces are not needed, data bit errors

or non-compliant operation can be tolerated, then domains can be grouped with digital IO 1.8-V power rail either directly or through an

in-line supply filter is allowed.

VDDA_0P8_<dll/pll> are 0.8-V analog domains supporting PLL and DLL circuitry needing a low noise supply for optimal performance.

It is not recommended to combine these domains with any other 0.8-V domains since high frequency switching noise could negatively

impact jitter performance of PLL and DLL signals.

VDD_MCU is a digital voltage domain with a wide range enabling it to be grouped and ramped-up with either 0.8-V VDD_CORE or

0.85-V RAM array (VDDAR_xxx) domains.

MCU_PORz and PORz must be asserted low for TΔ1 = 200 us MIN to ensure SoC resources enter into safe state before any voltage

begins to ramp down.

Figure 7-4. Combined MCU and Main Domains, Primary Power-Down Sequence

TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1

SPRSP62 – DECEMBER 2022

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TDA4VL...ALZQ1 数据表(PDF) 120 Page - Texas Instruments