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KSZ9563R 数据表(PDF) 178 Page - Microchip Technology |
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KSZ9563R 数据表(HTML) 178 Page - Microchip Technology |
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178 / 226 page  KSZ9563R DS00002419D-page 178 2017-2018 Microchip Technology Inc. 5.2.11.6 Port PTP Egress Timestamp for Sync High Word Register 5.2.11.7 Port PTP Egress Timestamp for Sync Low Word Register 5.2.11.8 Port PTP Egress Timestamp for PDelay_Resp High Word Register 5.2.11.9 Port PTP Egress Timestamp for PDelay_Resp Low Word Register Address: 0xNC0C - 0xNC0D Port N: 1-3 Size: 16 bits Bits Description Type Default 15:0 PTP Port N Egress Timestamp for Sync in Nanoseconds (SYNC_TS[31:16]) This field contains the Port N egress timestamp high-word value for the Sync frame in nanoseconds. RO 0x0000 Address: 0xNC0E - 0xNC0F Port N: 1-3 Size: 16 bits Bits Description Type Default 15:0 PTP Port N Eg0ss Timestamp for Sync in Nanoseconds (SYNC_TS[15:16]) This field contains the Port N egress timestamp low-word value for the Sync frame in nanoseconds. RO 0x0000 Address: 0xNC10 - 0xNC11 Port N: 1-3 Size: 16 bits Bits Description Type Default 15:0 PTP Port N Egress Timestamp for Pdelay_Resp in Nanoseconds (PDLY_TS[31:16]) This field contains the Port N egress timestamp high-word value for the Pde- lay_Resp frame in nanoseconds. RO 0x0000 Address: 0xNC12 - 0xNC13 Port N: 1-3 Size: 16 bits Bits Description Type Default 15:0 PTP Port N Egress Timestamp for Pdelay_Resp in Nanoseconds (PDLY_TS[15:0]) This field contains the Port N egress timestamp low-word value for the Pde- lay_Resp frame in nanoseconds. RO 0x0000 |
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