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KSZ9563R 数据表(PDF) 68 Page - Microchip Technology |
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KSZ9563R 数据表(HTML) 68 Page - Microchip Technology |
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68 / 226 page  KSZ9563R DS00002419D-page 68 2017-2018 Microchip Technology Inc. 5.1.1.10 Global Port Interrupt Mask Register This register enables the interrupts in the Global Port Interrupt Status Register. 5.1.2 GLOBAL I/O CONTROL REGISTERS (0x0100 - 0x01FF) 5.1.2.1 Serial I/O Control Register Address: 0x001C - 0x001F Size: 32 bits Bits Description Type Default 31:3 RESERVED RO - 2 Port 3 Interrupt Mask 0 = Interrupt enabled 1 = Interrupt disabled R/W 0b 1 Port 2 Interrupt Mask 0 = Interrupt enabled 1 = Interrupt disabled R/W 0b 0 Port 1 Interrupt Mask 0 = Interrupt enabled 1 = Interrupt disabled R/W 0b Address: 0x0100 Size: 8 bits Bits Description Type Default 7:3 RESERVED R/W 0100_0b 2 MIIM Preamble Suppression This feature affects only the MIIM (MDIO / MDC) interface. When using SPI or I2C, this bit has no effect. 0 = Normal operation. The switch always expects the MIIM preamble. 1 = The switch will respond to MIIM commands even in the absence of a preamble. R/W 0b 1 Automatic SPI Data Out Edge Select When enabled, this feature automatically determines the edge of SCL that is used to clock out the SPI data on SDO. If SCL ≥ ~25MHz, SDO data is clocked by the rising edge of SCL. If SCL < ~25 MHz, SDO data is clocked by the falling edge of SCL. 0 = The automatic feature is disabled, and bit 0 determines the SCL clock edge used for SDO. 1 = The automatic feature is enabled, and bit 0 is ignored. R/W 1b 0 SPI Data Out Edge Select When bit 1 is zero, then this bit determines the clock edge used for SPI data out. When bit 1 is set to 1, this bit is ignored. 0 = SDO data is clocked by the falling edge of SCL 1 = SDO data is clocked by the rising edge of SCL R/W 0b |
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