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KSZ9563R 数据表(PDF) 67 Page - Microchip Technology |
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KSZ9563R 数据表(HTML) 67 Page - Microchip Technology |
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67 / 226 page  2017-2018 Microchip Technology Inc. DS00002419D-page 67 KSZ9563R 5.1.1.8 Global Interrupt Mask Register This register enables the interrupts in the Global Interrupt Status Register. 5.1.1.9 Global Port Interrupt Status Register This register provides the top level interrupt status for the individual ports. These interrupts are enabled in the Global Port Interrupt Mask Register. Refer to the Port Interrupt Status Register for detailed port interrupt status. Address: 0x0014 - 0x0017 Size: 32 bits Bits Description Type Default 31 Lookup Engine (LUE) Interrupt Mask 0 = Interrupt enabled 1 = Interrupt disabled R/W 0b 30 GPIO Pin Output Trigger and Timestamp Unit Interrupt Mask 0 = Interrupt enabled 1 = Interrupt disabled R/W 0b 29:0 RESERVED RO - Address: 0x0018 - 0x001B Size: 32 bits Bits Description Type Default 31:3 RESERVED RO - 2 Port 3 Interrupt Status 0 = No interrupt 1 = Interrupt request RO 0b 1 Port 2 Interrupt Status 0 = No interrupt 1 = Interrupt request RO 0b 0 Port 1 Interrupt Status 0 = No interrupt 1 = Interrupt request RO 0b |
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