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KSZ9563R 数据表(PDF) 132 Page - Microchip Technology |
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KSZ9563R 数据表(HTML) 132 Page - Microchip Technology |
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132 / 226 page  KSZ9563R DS00002419D-page 132 2017-2018 Microchip Technology Inc. 5.2.1.12 Port Interrupt Mask Register This register enables the interrupts in the Port Interrupt Status Register. 0 ACL Interrupt Status ACL interrupts can be generated by configuring an entry in the ACL Table for counter mode. All ports have an ACL Table. To clear this bit, toggle the ACL Interrupt Mask bit in the Port Interrupt Mask Register. 0 = No interrupt 1 = Interrupt detected RO 0b Address: 0xN01F Port N: 1-3 Size: 8 bits Bits Description Type Default 7:3 RESERVED RO 0000_00b 2 PTP Interrupt Enable Applies only to PHY ports. Refer to the Port PTP Timestamp Interrupt Enable Register for individual PTP interrupt enables. 0 = Interrupt enabled 1 = Interrupt disabled R/W 0b 1 PHY Interrupt Enable Applies only to PHY ports. 0 = Interrupt enabled 1 = Interrupt disabled R/W 0b 0 ACL Interrupt Enable Applies to all ports. 0 = Interrupt enabled 1 = Interrupt disabled R/W 0b Bits Description Type Default |
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