KSZ9563R datasheet(151/226 Pages) MICROCHIP

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DS00002419D-page 151

KSZ9563R

5.2.3.2

XMII Port Control 1 Register

Note 5-5

The default value of this field is determined by the LED2_1 configuration strap value. Refer to Section

3.2.1, "Configuration Straps," on page 16 for additional information.

Note 5-6

The default value of this field is determined by the LED2_0 configuration strap value. Refer to Section

3.2.1, "Configuration Straps," on page 16 for additional information.

Note 5-7

The default value of this field is determined by the RXD[3:2] configuration strap value. Refer to

Section 3.2.1, "Configuration Straps," on page 16 for additional information.

Address:

0xN301

Port N: 3

Size:

8 bits

Bits

Description

Type

Default

RESERVED

R/W

Port Speed 1000

1 = RGMII operates at 1000 Mb/s

0 = RGMII operates at 10 or 100 Mb/s, as determined by bit 4 in the XMII Port

Control 0 Register

R/W

Note 5-5

RESERVED

R/W

RGMII Ingress Internal Delay (RGMII_ID_ig)

1 = Minimum 1.5 ns delay is added to ingress RGMII clock

0 = No delay is added

R/W

RGMII Egress Internal Delay (RGMII_ID_eg)

1 = Minimum 1.5 ns delay is added to egress RGMII clock

0 = No delay is added

R/W

MII / RMII / RGMII Modes

For MII interface:

1 = The MII interface operates as a MAC device (receives clocks, etc.)

0 = The MII interface operates as a PHY device (drives clocks, etc.)

For RMII interface:

1 = The 50 MHz RMII REFCLK is received at the RXC pin

0 = A 50 MHz RMII REFCLK is generated from the RXC pin

For RGMII interface:

1 = In-Band Status enabled. Requires connection to a IBS capable PHY.

0 = In-Band Status disabled.

R/W

Note 5-6

1:0

Port Interface Type Select

00 = Interface is MII

01 = Interface is RMII

10 = Interface is Reserved

11 = Interface is RGMII

R/W

Note 5-7

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