KSZ9567RTXI datasheet(57/232 Pages) MICROCHIP

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KSZ9567R

• Receipt of a Magic Packet

There are also other types of Wake-Up events that are not listed here as manufacturers may choose to implement these

in their own way.

4.10.5.1

Direction of Energy

The energy is detected from the cable and is continuously presented for a time longer than pre-configured value, espe-

cially when this energy change may impact the level at which the system should re-enter to the normal power state.

4.10.5.2

Direction of Link-up

Link status wake events are useful to indicate a linkup in the network's connectivity status.

4.10.5.3

Magic PacketTM

The Magic Packet is a broadcast frame containing anywhere within its payload 6 bytes of all 1s (FF FF FF FF FF FF)

followed by sixteen repetitions of the target computer's 48-bit DA MAC address. Since the magic packet is only scanned

for the above string, and not actually parsed by a full protocol stack, it may be sent as any network- and transport-layer

protocol.

Magic Packet technology is used to remotely wake up a sleeping or powered-off PC on a LAN. This is accomplished by

sending a specific packet of information, called a Magic Packet frame, to a node on the network. When a PC capable

of receiving the specific frame goes to sleep, it enables the Magic Packet RX mode in the LAN controller, and when the

LAN controller receives a Magic Packet frame, it will alert the system to wake up. Once the device has been enabled

for Magic Packet Detection, it scans all incoming frames addressed to the node for a specific data sequence, which

indicates to the controller this is a Magic Packet frame.

A Magic Packet frame must also meet the basic requirements for the LAN technology chosen, such as Source Address

(SA), Destination Address (DA), which may be the receiving station's IEEE MAC address, or a multicast or broadcast

address and CRC. The specific sequence consists of 16 duplications of the MAC address of this node, with no breaks

or interruptions. This sequence can be located anywhere within the packet, but must be preceded by a synchronization

stream. The synchronization stream is defined as 6 bytes of 0xFF. The device will also accept a broadcast frame, as

long as the 16 duplications of the IEEE address match the address of the machine to be awakened.

4.10.5.4

Interrupt Generation on Power Management Related Events

There are two ways an interrupt can be generated to the host whenever a power management related event takes place.

The resulting interrupts are via the PME_N signal pin or via the INTRP_N signal pin.

4.11

Management Interface

The management interface may be used by an external host processor to read and write the device’s registers. This

interface has three available modes of operation: SPI, I2C or MIIM. The interface mode is selected at the deassertion

of reset by a strapping option (refer to Section 3.2.1, "Configuration Straps," on page 16 for additional information).

Of the three interface options, SPI provides the highest performance, while MIIM performance is the lowest. Most impor-

tantly, MIIM provides access to the PHY control and status registers, but not to any of the switch registers. The vast

majority of applications therefore can use SPI or I2C, but not MIIM.

4.12, "In-Band Management," on page 61.

4.11.1

SPI SLAVE BUS

The KSZ9567R supports a slave mode SPI interface that provides complete access to all device registers via an SPI

master device. The SPI master device supplies the clock (SCL), select (SCS_N), and serial input data (SDI). Serial out-

put data (SDO) is driven by the KSZ9567R.

SCL is expected to stay low when SPI operation is idle. SPI operations start with the falling edge of SCS_N and end with

the rising edge of SCS_N. A single read or write access consists of a 27-bit command/address phase, then a 5-bit turn-

around (TA) phase, then an 8-bit data phase. For burst read or write access, SCS_N is held low while SCL continues to

toggle. For every 8 cycles of SCL, the device will increment the address counter, and the corresponding data byte will

be transferred on SDI or SDO in succession.

All commands, addresses and data are transferred most significant bit first. Input data on SDI is latched on the rising

edge of clock SCL. Output data on SDO is clocked on the falling edge of SCL.

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