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KSZ9567RTXI 数据表(PDF) 93 Page - Microchip Technology |
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KSZ9567RTXI 数据表(HTML) 93 Page - Microchip Technology |
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93 / 232 page  2017-2019 Microchip Technology Inc. DS00002329D-page 93 KSZ9567R 5.1.4.28 Switch MAC Control 5 Register 5.1.4.29 Switch MIB Control Register MIB counters are provided on a per-port basis. They are read and controlled via the Port N: Port Switch MIB Counters Registers (0xN500 - 0xN5FF). 5.1.4.30 802.1p Priority Mapping 0 Register Address: 0x0335 Size: 8 bits Bits Description Type Default 7 RESERVED RO 0b 6 RESERVED R/W 0b 5:4 Ingress Rate Limit Period 00 = 16ms 01 = 64ms 1x = 256ms R/W 01b 3 Queue Based Egress Rate Limit Enable 1 = Queue-based egress rate limiting 0 = Port-based egress rate limiting R/W 0b 2:0 RESERVED RO 000b Address: 0x0336 Size: 8 bits Bits Description Type Default 7 Flush MIB Counters 1 = Flush all MIB counters of enabled ports. Refer to the Port MIB Control and Status Register. 0 = Normal counter operation R/W SC 0b 6 Freeze MIB Counters 1 = Freeze MIB counters of enabled ports. Refer to the Port MIB Control and Status Register. 0 = Normal counter operation R/W 0b 5:0 RESERVED RO 00_0000b Address: 0x0338 Size: 8 bits Bits Description Type Default 7 RESERVED RO 0b 6:4 When the tag PCP field is 0x1, use this value for priority R/W 001b 3 RESERVED RO 0b 2:0 When the tag PCP field is 0x0, use this value for priority R/W 000b |
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