KSZ9567RTXI datasheet(63/232 Pages) MICROCHIP

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DS00002329D-page 63

KSZ9567R

4.13.1

MEDIA INDEPENDENT INTERFACE (MII)

The media independent interface (MII) is specified in Clause 22 of the IEEE 802.3 standard. It provides a common inter-

face between PHY layer and MAC layer devices. The data interface is 4-bits wide and runs at one quarter the network

bit rate; either 2.5MHz in 10BASE-Te or 25MHz in 100BASE-TX (not encoded). Additional signals on the transmit side

indicate when data is valid or when an error occurs during transmission. Similarly, the receive side provides signals that

convey when the data is valid and without physical layer errors. For half duplex operation, the COL signal indicates if a

collision has occurred during transmission.

Each MII interface operates in either PHY Mode or MAC Mode. Select PHY Mode when the port is connected to a pro-

cessor or other device with a MAC function; select MAC Mode when connecting to an external PHY. Note that the direc-

tion of the TX_CLKx, RX_CLKx, COLx and CRSx signals is affected by the PHY mode or MAC mode setting, while

other MII signals do not change direction.

MII mode is selected at reset by a configuration strap option on pins RXD6_3 and RXD6_2 for port 6, and pins RXD7_3

and RXD7_2 for port 7. The Speed strapping option (on pin RXD6_0 for port 6 and RXD7_0 for port 7) should be set for

100/10 Mbps Mode. PHY Mode or MAC Mode is selected by strapping option on pins RXD6_1 (port 6) and RXD7_1

(port 7). Refer to Section 3.2.1, "Configuration Straps," on page 16 for additional information.

The interface contains two distinct groups of signals, one for transmission and the other for reception. Table 4-28 and

Table 4-29 describe the signals used by the MII interface to connect to an external MAC or to an external PHY, respec-

tively.

4.13.2

REDUCED MEDIA INDEPENDENT INTERFACE (RMII)

The reduced media independent interface (RMII) specifies a low pin count interface, which is based on MII, that provides

communication with a MAC attached to the port. As with MII, RMII provides a common interface between physical layer

and MAC layer devices, or between two MAC layer devices, and has the following key characteristics:

TABLE 4-28:

MII (PHY MODE) CONNECTION TO EXTERNAL MAC

MII Interface Signals Description

KSZ9567R Signals in PHY Mode

External MAC Device Signals

Transmit Enable

TX_ENx (input)

TX_EN (output)

Transit Error

TX_ERx (input)

TX_ER (output)

Transmit Data Bits [3:0]

TXDx_[3:0] (input)

TXD[3:0] (output)

Transmit Clock

TX_CLKx (output)

TX_CLK (input)

Collision Detection

COLx (output)

COL (input)

Carrier Sense

CRSx (output)

CRS (input)

Received Data Valid

RX_DVx (output)

RX_DV (input)

Receive Error

RX_ERx (output)

RX_ER (input)

Receive Data Bits [3:0]

RXDx_[3:0] (output)

RXD[3:0] (input)

Receive Clock

RX_CLKx (output)

RX_CLK (input)

TABLE 4-29:

MII (MAC MODE) CONNECTION TO EXTERNAL PHY

MII Interface Signals Description

KSZ9567R Signals in MAC Mode

External PHY Device Signals

Transmit Enable

RX_DVx (output)

TX_EN (input)

Transit Error

RX_ERx (output)

TX_ER (input)

Transmit Data Bits [3:0]

RXDx_[3:0] (output)

TXD[3:0] (input)

Transmit Clock

RX_CLKx (input)

TX_CLK (output)

Collision Detection

COLx (input)

COL (output)

Carrier Sense

CRSx (input)

CRS (output)

Received Data Valid

TX_ENx (input)

RX_DV (output)

Receive Error

TX_ERx (input)

RX_ER (output)

Receive Data Bits [3:0]

TXDx_[3:0] (input)

RXD[3:0] (output)

Receive Clock

TX_CLKx (input)

RX_CLK (output)

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