KSZ9567RTXI datasheet(157/232 Pages) MICROCHIP

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DS00002329D-page 157

KSZ9567R

5.2.4.3

Port Ingress Rate Limit Control Register

Address:

0xN403

Port N: 1-7

Size:

8 bits

Bits

Description

Type

Default

RESERVED

Port or Priority Based Ingress Rate Limiting

1 = Ingress rate limiting is port based

0 = Ingress rate limiting is priority based

R/W

Ingress PPS Mode

1 = Ingress rate limiting is based on number of packets (PPS mode enabled)

0 = Ingress rate limiting is based on number of bits (PPS mode disabled)

R/W

Ingress Rate Limit Flow Control Enable

To use this feature, flow control must also be enabled for this port. Refer to

the XMII Port Control 0 Register for non-PHY ports, and the PHY Auto-

Negotiation Advertisement Register for PHY ports.

1 = Flow control is asserted if the port’s receive rate is exceeded

0 = Flow control is not asserted based on ingress rate limits

R/W

3:2

Ingress Limit Mode

These bits determine what kind of frames are limited and counted against

ingress rate limiting.

00 = Count and limit all frames

01 = Count and limit broadcast, multicast and flooded unicast frames only

10 = Count and limit broadcast and multicast frames only

11 = Count and limit broadcast frames only

R/W

00b

Count IFG Bytes

1 = Each frame’s minimum inter-frame gap (IFG) bytes (12 per frame) are

included in ingress rate limiting calculations

0 = IFG byte count is not included

R/W

Count Preamble Bytes

Not valid when PPS mode is enabled (bit 5)

1 = Each frame’s preamble bytes (8 per frame) are included in ingress rate

limiting calculations

0 = Preamble byte count is not included

R/W

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