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STE2001

October 2001

This is preliminary information on a new product now in development. Details are subject to change without notice.

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65 x 128 bits Display Data RAM

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Configurable matrix: 65 x 128 or 33 x 128

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Programmable (65/33) MUX rate

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Row by Row Scrolling

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Automatic data RAM Blanking procedure

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Selectable Input Interface:

• Parallel Interface (write only)

• Serial Interface (write only)

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Fully Integrated Oscillator requires no external

components

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Fully Integrated Configurable LCD bias voltages

generator with:

• Effective sensing for High Precision Output

• Four selectable temperature compensation

coefficients

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Designed for chip-on-glass (COG) applications

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Programmable bottom row pads mirroring and

top row pads mirroring for compatible with both

TCP and COG applications

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Low Power Consumption, suitable for battery

operated systems

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Logic Supply Voltage range from 1.9 to 5V

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High Voltage Generator Supply Voltage range

from 2.4 to 4.5V

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Display Supply Voltage range from 4.5 to 9V

DESCRIPTION

The STE2001 is a low power CMOS LCD controller

driver. Designed to drive a 65 rows by 128 columns

graphic display, provides all necessary functions in a

single chip, including on-chip LCD supply and bias

voltages generators, resulting in a minimum of exter-

nals components and in a very low power consump-

tion. The STE2001 features three standard interfaces

host

Type

Ordering Number

Bumped Wafers

STE2001DIE1

Bumped Dice on Waffle Pack

STE2001DIE2

PRODUCT PREVIEW

65 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER

Figure 1. Block Diagram

COLUMN

DRIVERS

ROW

DRIVERS

DATA

LATCHES

65 x 128

RAM

DISPLAY

CONTROL

LOGIC

SCROLL

LOGIC

DATA

REGISTER

I2CBUS

INSTRUCTION

REGISTER

OSC

CO to C127

R0 to R64

OSC

VLCDIN

VLCDSENSE

RES

VDD1,2,3

CLOCK

TIMING

GENERATOR

BIAS VOLTAGE

GENERATOR

HIGH VOLTAGE

GENERATOR

RESET

TEST

SHIFT

REGISTER

VLCDOUT

SEL1,2

SAO

TEST_0_13

SDA_IN

SDA_OUT

SCL

DB0 to DB7 E

PD/C

PARALLEL

SERIAL

D00IN1137

SCE

SDIN

SCLK

SD/C

BSY_FLG