STE2001

18/36

Communication Protocol

The STE2001 is an I

Two are the devic e addresses availabl e for the device. Both have in common the first 6 bits (011110). The least sig-

nifica nt bit of the slave address is set by connecting the SA0 input to a logic 0 or to a logic 1.

To start the communication between the bus master and the slav e LCD driver, the master must initiate a START con-

dition. Followin g this, the master sends an 8-bit byte, shown in Fig. 18, on the SDA bus line (Most signif icant bit first).

This consists of the 7-bit Device select Code, and the 1-bit Read/Write Designator (R/

W).

All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I

Writing Mode.

If the R/W bit is set to logic 0 the STE2001 is set to be a receiver. After the slaves acknowledge one or more

command word follows to define the status of the device.

A command word is composed by two bytes. The first is a control byte which defines the Co and D/C values,

the second is a data byte (fig 18). The Co bit is the command MSB and defines if after this command will follow

one data byte and an other command word or if will follow a stream of data (Co = 1 Command word, Co = 0

Stream of data). The D/C bit defines whether the data byte is a command or RAM data (D/C = 1 RAM Data, D/

C = 0 Command).

If Co =1 and D/C = 0 the incoming data byte is decoded as a command, and if Co =1 and D/C =1, the following

data byte will be stored in the data RAM at the location specified by the data pointer.

E very byte of a command word must be acknowledged by all addressed units.

After the last control byte, if D/C is set to a logic 1 the incoming data bytes are stored inside the STE2001 Display

RAM starting at the address specified by the data pointer. The data pointer is automatically updated after every

byte written and in the end points to the last RAM location written.

Every byte must be acknowledged by all addressed units.

Reading Mode.

If the R/W bit is set to logic 1 the chip will output data immediately after the slave address. If the D/C bit sent

during the last write access, is set to a logic 0, the byte read is the status byte.

START

CLOCK PULSE FOR

ACKNOWLEDGEMENT

DATA OUTPUT

BY RECEIVER

SCLK FROM

MASTER

DATA OUTPUT

BY TRANSMITTER

D00IN1152

1

MSB

LSB

28

9

Sr

SCLH

RES

SDAH

D00IN1153

Sr P

(1)

(1)

= MCS current source pull-up

= Rp resistor pull-up