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STE2001 数据表(PDF) 4 Page - STMicroelectronics |
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STE2001 数据表(HTML) 4 Page - STMicroelectronics |
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4 / 36 page ![]() STE2001 4/36 Notes: 1. The maximum possible VLCD voltage that can be generated is dependent on voltage, temperature and (display) load. 2. Internal clock 3. When fsclk = 0 there is no interface clock. 4. Power-down mode. During power-down all static currents are switched-off. 5. If external VLCD, the display load current is not transmitted to IDD 6. Tolerance depends on the temperature; (typically zero at Tamb =27°C), maximum tolerance values are measured at the temper- ature range limit. 7. For TC0 to TC3 AC OPERATION (VDD1 = 1.9 to VDD2,3 + 0.5V; VDD2,3 = 2.4 to 4.5 V; Vss1,2= 0V; VLCD = 4.5 to 9V; Tamb =-40 to 85°C; unless otherwise specified) I(VDD1,2,3) Total Supply Current VLCD = 7.6V; VDD =2.8V; 4x charge pump; fsclk =0; Tamb =25 °C; no display load; note 3,6 Fosc =0 80 125 µA I(VLDCIN) External LCD Supply Voltage Current VDD =2.8V; VLCD =7.6V;no display load; fsclk =0; Tamb =25°C; note 3. Fosc =0 15 25 µA Logic Inputs VIL Logic LOW voltage level VIN =Vih (tp <10µs) VSS 0.3 VDD V VIH Logic HIGH Voltage Level VIN =Vil (tp <10µs) 0.7 VDD VDD2,3 +0.5 V Iin Input Current Vin =VSS1 or VDD1 -1 1 µA Column and Row Driver Rrow ROW Output Resistance 12 20 kohm Rcol Column Output resistance 12 20 kohm Vcol Column Bias voltage accuracy No load -100 100 mV Vrow Row Bias voltage accuracy -100 100 mV LCD Supply Voltage VLCD LCD Supply Voltage accuracy; Internally generated VDD = 2.8V; VLCD = 7.6V; fsclk=0; Tamb=25 C; no display load; note 2, 3, 6 & 7 -300 300 mV TC Temperature coefficient 00 -550 PPM/ °C 01 -1350 PPM/ °C 10 -1650 PPM/ °C 11 -2650 PPM/ °C Symbol Parameter Test Condition Min. Typ. Max. Unit INTERNAL OSCILLATOR FOSC Internal Oscillator frequency VDD = 2.8V; 20 38 70 kHz FEXT External Oscillator frequency 20 38 100 kHz Symbol Parameter Test Condition Min. Typ. Max. Unit ELECTRICAL CHARACTERISTICS (continued) |
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