STE2001

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The end of the procedure will be notified on the BSY_FLG pad going HIGH, while LOW the procedure is running.

Any instruction programmed with BSY_FLG LOW will be ignored, that is, no instruction can be programmed for

a period equivalent to 128X9 internal write cycles (128X9X1/fclock). The start of Memory blanking procedure

will be between one and two fclock cycles from the last active edge (E rising edge for the parallel interface, last

Scroll

The STE2001 can scroll the graphics display in units of raster-rows. The scrolling function is achieved changing

the correspondence between the rows of the logical memory map and the output row drivers. The scroll function

doesn’t affect the data ram content. It is only related to the visualization process. The information output on the

drivers is related to the row reading sequence (the 1st row read is output on R0, the 2nd on R1 and so on).

Scrolling means reading the matrix starting from a row that is sequentially increased or decreased. After every

scrolling command the offset between the memory address and the memory scanning pointer is increased or

decreased by one. The offset range is between 0 to 63 in mux 65 mode and 0-31 in mux 33 mode. After the

64th scrolling command in mux 65 mode and after the 32th in mux 33 mode, the offset between the memory

address and the memory scanning pointer is again zero (Cyclic Scrolling). Bank8 is always accessed last in

each frame, and so isn’t scrolled.

If the DIR Bit is set to a logic zero the offset register is increased by one and the raster is scrolled from top down. If

the DIR Bit is set to a logic one the offset register is decreased by one and the raster is scrolled from bottom-up.

Bus Interfaces

To provide the widest flexibility and ease of use the STE2001 features three different methods for interfacing

the host Controller. To select the desired interface the SEL1 and SEL2 pads need to be connected to a logic

LOW (connect to GND) or a logic HIGH (connect to VDD). All the I/O pins of the unused interfaces must be

connected to GND. If I/O pins voltage is lower than VDD interfaces could sink more current than expected.

All interfaces are working while the STE2001 is in Power Down.

I

The I

High Speed Mode (3.4MHz).

This bus is intended for communication between different Ics. It consists of two lines: one bi-directional for data

signals (SDA) and one for clock signals (SCL). Both the SDA and SCL lines must be connected to a positive

supply voltage via an active or passive pull-up.

The following protocol has been defined:

- Data transfer may be initiated only when the bus is not busy.

- During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line

while the clock line is high will be interpreted as control signals.

Accordingly, the following bus conditions have been defined:

BUS not busy: Both data and clock lines remain High.

Start Data Transfer: A change in the state of the data line, from High to Low, while the clock is High, define the

START condition.

SEL2

SEL1

Interface

Note

00

Read and Write; Fast and

High Speed Mode

0

1

Serial

Write only

1

1

Parallel

Write only

1

0

Not Used