11/36

STE2001

Figure 11. Output drivers rows and logical memory rows correspondence with MY = 0

Figure 12. Output drivers rows and logical memory rows correspondence with MY = 1

Instruction Set

Two different instructions formats are provided:

- With D/C set to LOW

commands are sent to the Control circuitry.

- With D/C set to HIGH

the Data RAM is addressed Instructions have the syntax summarized in Table.1.

Reset (RES)

At power-on, all internal registers and RAM content are not defined. A Reset pulse must be applied on RES pad

(active low) to initialize the internal registers content (see Tables 3,4,5,&6). Every on-going communication with

the host controller is interrupted. The IC after the reset pulse is programmed in Power Down mode.

The Default configurations is:

- Horizontal addressing (V = 0)

- Normal instruction set (H = 0)

- Normal display (MX = MY = TRS =BRS = 0)

- MUX 65 mode (MUX = 0)

D00IN1148

R16

to

R23

Row 0

to

Row 7

BANK 4

BANK 5

BANK 6

BANK 7

BANK 8

01

23

45

67

123 124 125

121 122

120

126 127

ROW DRIVER

MUX 33 PHYSICAL MEMORY ROW

R24

to

R31

Row 8

to

Row15

R48

to

R55

Row 16

to

Row 23

R56

to

R63

Row 24

to

Row 31

R64

Row 32

D00IN1148

R16

to

R23

Row 0

to

Row 7

BANK 4

BANK 5

BANK 6

BANK 7

BANK 8

01

23

45

67

123 124 125

121 122

120

126 127

ROW DRIVER

MUX 33 PHYSICAL MEMORY ROW

R24

to

R31

Row 8

to

Row15

R48

to

R55

Row 16

to

Row 23

R56

to

R63

Row 24

to

Row 31

R64

Row 32