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STE2001

Figure 19. communication protocol

SERIAL INTERFACE

The STE2001 serial Interface is a unidirectional link between the display driver and the application supervisor.

It consists of four lines: one for data signals (SDIN), one for clock signals (SCLK), one for the peripheral enable

(SCE) and one for mode selection (SD/C).

The serial interface is active only if the SCE line is set to a logic 0. When SCE line is high the serial peripheral

power consumption is zero.

The STE2001 is always a slave on the bus and receive the communication clock on the SCLK pin from the mas-

ter. The STE2001 is only able to receive data.

Information are exchanged byte-wide. During data transfer, the data line is sampled on the positive SCLK edge.

While SCE pin is high the serial interface is kept in reset.

SD/C line status indicates whether the byte is a command (SD/C =0) or RAM data (SD/C =1);it is read on the

eighth SCLK clock pulse during every byte transfer.

If SCE stays low after the last bit of a command/data byte, the serial interface expects the MSB of the next byte

at the next SCLK positive edge.

A reset pulse on RES pin interrupts the transmission. No data is written into the data RAM and all the internal

registers are cleared.

If SCE is low after the positive edge of RES, the serial interface is ready to receive data.

S

S

011110

0

A0 A

STE2001 ACK

WRITE MODE

READ MODE

R/W

R/W

SLAVE ADDRESS

Co

STE2001 ACK

COMMAND WORD

CONTROL BYTE

MSB........LSB

Co

LAST

N> 0 BYTE

STE2001 ACK

STE2001 ACK

STE2001 ACK

A

1 DC Control Byte

DATA Byte

A

DC Control Byte

A 0

DATA Byte

A P

S

S

011110

0

A1 A

STE2001 ACK

MASTER

P

STE2001

SLAVE ADDRESS

S

011110

0

A

R

/

W

CONTROL BYTE

C

o

D

C

0 00000 A

D01IN1247